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Visitor kikilinux
Visitor
2,479 Views
Registered: ‎04-16-2014

ERROR:EDK - while loading XMP file

Hi all,
Can someone please help me with these errors:


[root@localhost loopback_test_nf1_cml]# make
make -C hw bits
make[1]: Entering directory `/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw'
xps -nw -scr genmakes.tcl

Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

XPS% Evaluating file genmakes.tcl
ERROR:EDK - IPNAME: axi_interconnect, INSTANCE:
axi_interconnect_memory_mapped_lite_0 - PORT interconnect_aclk not found in
the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 46 
ERROR:EDK - IPNAME: axi_interconnect, INSTANCE:
axi_interconnect_memory_mapped_lite_0 - PORT INTERCONNECT_ARESETN not found
in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 47 
ERROR:EDK - IPNAME: axi_interconnect, INSTANCE:
axi_interconnect_memory_mapped_lite_0 - PARAMETER
C_INTERCONNECT_CONNECTIVITY_MODE not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 45 
ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block -
BUS_INTERFACE PORTA not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 112 
ERROR:EDK - IPNAME: bram_block, INSTANCE: microblaze_0_bram_block -
BUS_INTERFACE PORTB not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 113 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - BUS_INTERFACE S_AXI
not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 139 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT TX not found in
the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 140 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT RX not found in
the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 141 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PORT S_AXI_ACLK not
found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 142 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BAUDRATE
not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 133 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_DATA_BITS
not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 134 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER
C_USE_PARITY not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 135 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER
C_ODD_PARITY not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 136 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_BASEADDR
not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 137 
ERROR:EDK - IPNAME: axi_uartlite, INSTANCE: RS232_Uart_1 - PARAMETER C_HIGHADDR
not found in the MPD -
/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw/system.m
hs line 138 
ERROR:EDK - while loading XMP file
make[1]: *** [system.make] Error 1
make[1]: Leaving directory `/home/karin/NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml/hw'
make: *** [all] Error 2

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2 Replies
Xilinx Employee
Xilinx Employee
2,466 Views
Registered: ‎07-01-2010

Re: ERROR:EDK - while loading XMP file

Hi,

It looks like you are trying to migrate the design from old version to the newer version , is this correct?

 

Refer to the AR#32143 which explains the steps to migrate the design  http://www.xilinx.com/support/answers/32143.htm

 

Hope this helps.

Regards,
Achutha

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Xilinx Employee
Xilinx Employee
2,462 Views
Registered: ‎08-02-2007

Re: ERROR:EDK - while loading XMP file

Hi,

 

I think you are adding interconnect, BRAM and UART for an existing system. The IP's that are shown in the error do not seem to be configured. So i would recommend you to configure the IP's first and then do a Project --> Design Rule Check to confirm if you are good to go to implement the design.

 

An easier way to do this is to create a blank project and then adding up your peripherals.

 

--Hem

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