UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor ruizmartinez
Visitor
2,352 Views
Registered: ‎10-28-2009

ERROR:Route:537 - A core generated by the Memory Interface Generator (MIG) has been detected in this design

 Hi I have this problem when I try to implement my dsign with a memory controller implemented with MIG.

 

Phase  1  : 7539 unrouted;      REAL time: 10 secs
ERROR:Route:537 -  A core generated by the Memory Interface Generator (MIG) has been detected in this design  but PAR is unable to route the critical signals of this core to meet the necessary skew and delay  requirements. Please ensure that there are no location constraints or Directed Routing constraints   on the MIG core logic/routes that could conflict with automatic placement and routing. To generate   an NCD that can be used for debugging in FPGA Editor, please re-run PAR with the environme
nt variable  XIL_PAR_DISABLE_MIG_ANALYSIS 1. Note that if this NCD is used, the design can fail in hardware.   Below is the list of nets in which PAR had problems routing optimally:

|======================================================================|
|----------------------------------------------------------------------
| Sig: u_mem_controller/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[0].u_iob_dq/stg1_out_rise_sg1
| Sig: u_mem_controller/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[0].u_iob_dq/stg1_out_fall_sg1
| Sig: u_mem_controller/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/stg1_out_rise_sg1
|----------------------------------------------------------------------
|----------------------------------------------------------------------
| Sig: u_mem_controller/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[4].u_iob_dq/stg1_out_rise_sg1
|----------------------------------------------------------------------
|----------------------------------------------------------------------
| Sig: u_mem_controller/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[7].u_iob_dq/stg1_out_rise_sg1
|----------------------------------------------------------------------
|======================================================================|


Process "Place & Route" failed

 

Thank you very much for your help.

 

Emilio

0 Kudos