ERROR:Route:537 - A core generated by the Memory Interface Generator (MIG) has been detected in this design
Hi I have this problem when I try to implement my dsign with a memory controller implemented with MIG.
Phase 1 : 7539 unrouted; REAL time: 10 secs ERROR:Route:537 - A core generated by the Memory Interface Generator (MIG) has been detected in this design but PAR is unable to route the critical signals of this core to meet the necessary skew and delay requirements. Please ensure that there are no location constraints or Directed Routing constraints on the MIG core logic/routes that could conflict with automatic placement and routing. To generate an NCD that can be used for debugging in FPGA Editor, please re-run PAR with the environme nt variable XIL_PAR_DISABLE_MIG_ANALYSIS 1. Note that if this NCD is used, the design can fail in hardware. Below is the list of nets in which PAR had problems routing optimally: