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6,592 Views
Registered: ‎06-29-2009

Err. NgdBuild 604; custom IP; Tried many tricks on this forum

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Hi,

 

I did implement a custom IP to use in XPS.   When I runned the IP without modify the VHDL (user logic) with an extra module , then I had no problems.

After adding an sub-module to the User_logic.vhdl , then I got next error in XPS whil generating the bitstream:

 

 make: *** [__xps/system_routed] Error 1
ERROR:NgdBuild:604 - logical block
   'demoip_0/demoip_0/USER_LOGIC_I/ICAP_SP601_Reboot_inst' with type
   'ICAP_SP601_Reboot' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, or the misspelling of a type name. Symbol
   'ICAP_SP601_Reboot' is not supported in target 'spartan6'.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

 

I think I tried everything: ?

- cleanup in XPS

- cleanup in ISE

- make a new fresh IP and copy imediately my VHDL file, without opening ISE

- copy the ngc in the directory of custom to evry directory in custom IP (I don't know where I should copy this ngc file else)

- I used next link to hope to fix the problem.  I restarted XPS, cleaned the hardware and regenerate all, but still got the error.

lftp://ftp.xilinx.com/pub/applications/3rdparty/34179.zip

- I changed the name ICAP_SP601_REBOOT to reboot  (I thought this wouldn't help ... but din't knwo what else to try)

- when I comment the ICAP_REBOOT_INST then it goes well  =>  so think the problem is in the fact I ad a module ...

 

 

The purpose of the IP is to use the ICAP_reboot given in the reference design with microblaze  (after some modification) .

 

Is there another problem or setting  or did I do smt wrong in my code (when I synthesized and implement the design in ISE I had no error)?  It's strange coz for me it's like it is  threating the module like a primitive. 

 

 

 

The 2 VHDL code if necesary:

 

 

 

USER_LOGIC.VHDL :

 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;


entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 4
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic

 component ICAP_SP601_Reboot
 port  (   
        CLK : in std_logic;
      RESET : in std_logic;
        REBOOT : in std_logic;
      BUSY : out std_logic;
        DOUT: out std_logic_vector(15 downto 0));
end component;



  signal icapOut                        : std_logic_vector(0 to 15);
  signal icapIn                         : std_logic_vector(15 downto 0);
  signal icapWrite                      : std_logic;
  signal icapClk                           : std_logic;
  signal icapCE                         : std_logic;
  signal icapBusy                          : std_logic;
 
 
 
 
------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
 
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel              : std_logic_vector(0 to 3);
  signal slv_reg_read_sel               : std_logic_vector(0 to 3);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;
   
  signal CLK_wire                             : std_logic;
  signal MBT_RESET_wire                     :  std_logic;
  signal MBT_REBOOT_wire                     :  std_logic;
  signal MBT_BUSY_wire                         : std_logic;
  signal ICAP_DOUT_wire                        : std_logic_vector(15 downto 0);

begin


 

ICAP_SP601_Reboot_inst : ICAP_SP601_Reboot port map (

        CLK => Bus2IP_Clk,
      RESET => slv_reg0(0),
        REBOOT => slv_reg1(0),
      BUSY => MBT_BUSY_WIRE,
        DOUT => ICAP_DOUT_WIRE

);



  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  --
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  --
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  --
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "1000" =>
            for byte_index in 0 to 3 loop
             if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
                     slv_reg0(0) <= Bus2IP_Data(0);
                     
              end if;
            end loop;
           when "0100" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0010" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
             when "0001" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin

    case slv_reg_read_sel is
     
        when "1000" =>
           
  slv_ip2bus_data <= slv_reg0;
     
        when "0100" =>
            
slv_ip2bus_data <= slv_reg1;
              --icapBusy;
              -- slv_ip2bus_data(1 to 31) <= (others => '0');

       
      when "0010" =>
            
slv_ip2bus_data(16 to 31) <= ICAP_DOUT_WIRE;
             
              slv_ip2bus_data(0 to 15) <= (others => '0');

             
        when "0001" =>
            
           
  slv_ip2bus_data(31) <= MBT_BUSY_WIRE;

slv_ip2bus_data(0 to 30) <=    (others => '0');   
              --slv_ip2bus_data(0 to 15) <= icapOut(0 to 15);
             
             -- slv_ip2bus_data(16 to 31) <= (others => '0');
       
      when others => slv_ip2bus_data <= (others => '0');
   
     end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

end IMP;

 

 

 

 

 ICAP_SP06_REBOOT.VHDL

 

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ICAP_SP601_Reboot is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           reboot : in  STD_LOGIC;
           busy : out  STD_LOGIC;
           Dout : out  STD_LOGIC_VECTOR (15 downto 0));
end ICAP_SP601_Reboot;

architecture Behavioral of ICAP_SP601_Reboot is

component ICAP_SPARTAN6
port(
    BUSY   : out std_logic;   
    O      : out std_logic_vector(15 downto 0);   
    CE     : in std_logic;   
    CLK    : in std_logic;   
    I      : in std_logic_vector(15 downto 0);   
    WRITE  : in std_logic
);
end component;

signal w_ce : std_logic;
signal w_I, I_trans : std_logic_vector(15 downto 0);
signal w_write : std_logic;


type STATE_TYPE is (idle, SYNC_H, sync_L, cwd_H, cwd_L, nul_H, nul_l, mod_H, mod_L, hco_H, hco_L, Rbt_H, rbt_L, noop_0, noop_1, noop_2, noop_3 );

attribute ENUM_ENCODING: STRING;

attribute ENUM_ENCODING of STATE_TYPE:type is "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17";


signal CurS, NextS: STATE_TYPE;



begin


ICAP_SPARTAN3_Inst : Icap_Spartan6
port map(
    BUSY  => busy,
    O     => Dout,  
    CE    => w_ce,
    CLK   => clk,
    I     => I_trans,
    WRITE => w_write
);



StateSync: process(clk, reset)
begin
    if (reset = '1') then
        curS <= idle;
    elsif rising_edge(clk) then
      curS <= nextS;
   end if;
end process;


StateMachine : Process(curS, reboot)
begin

    case curS is
        when idle =>
               if (REBOOT = '1') then
                     nextS  <= SYNC_H;
                     w_ce   <= '0';
                     w_write  <= '0';
                     w_I    <= x"AA99";  --// Sync word part 1
               else
                     nextS  <= IDLE;
                     w_ce     <= '1';
                     w_write     <= '1';
                     w_I    <= x"FFFF";  -- Null data
                    end if;
         when SYNC_H =>
               nextS  <= SYNC_L;
               w_ce     <= '0';
               w_write  <= '0';
               w_I    <= x"5566";    --Sync word part 2
      
-- //--------------------

         when SYNC_L =>
               nextS  <= NUL_H;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"30A1";    --  Write to Command Register....

        when NUL_H =>
               nextS  <= NUL_L;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"0000";   --  Null Command issued....  value = 0x0000

-- //--------------------

        when NUL_L =>
               nextS  <= RBT_H;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"30A1";      --  Write to Command Register....

        when RBT_H =>
               nextS  <= RBT_L;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"000E";      -- REBOOT Command issued....  value = 0x000E
        

-- //--------------------

        when RBT_L =>
               nextS  <= NOOP_0;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"2000";    --  NOOP

        when NOOP_0 =>
               nextS  <= NOOP_1;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"2000";    -- NOOP

        when NOOP_1 =>
               nextS  <= NOOP_2;
               w_ce     <= '0';
               w_write    <= '0';
               w_I    <= x"2000";    -- NOOP

        when NOOP_2 =>
               nextS  <= NOOP_3;
               w_ce     <= '0';
               w_write     <= '0';
               w_I    <= x"2000";    -- NOOP
            

-- //--------------------

        when NOOP_3 =>
               nextS  <= IDLE;
               w_ce     <= '1';
               w_write     <= '1';
               w_I    <= x"1111";    -- NULL value
        
          
        when others =>
               nextS  <= IDLE;
               w_ce     <= '1';
               w_write     <= '1';
               w_I    <= x"1111";    --  16'h1111"

      end case;
 

end process;


translate_icap : process(clk)
begin
 if rising_edge(clk) then
       I_trans(0) <= w_I(7);
        I_trans(1) <= w_I(6);
        I_trans(2) <= w_I(5);
        I_trans(3) <= w_I(4);
        I_trans(4) <= w_I(3);
        I_trans(5) <= w_I(2);
        I_trans(6) <= w_I(1);
        I_trans(7) <= w_I(0);
        I_trans(8) <= w_I(15);
        I_trans(9) <= w_I(14);
        I_trans(10) <= w_I(13);
        I_trans(11) <= w_I(12);
        I_trans(12) <= w_I(11);
        I_trans(13) <= w_I(10);
        I_trans(14) <= w_I(9);
        I_trans(15) <= w_I(8);
        
 end if;
end process;


end Behavioral;

 

 

 

Message Edited by serge.kubera@ehb.be on 03-03-2010 07:19 PM
Message Edited by serge.kubera@ehb.be on 03-04-2010 11:47 AM
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Adventurer
Adventurer
8,204 Views
Registered: ‎08-19-2009

Re: Err. NgdBuild 604; custom IP; Tried many tricks on this forum

Jump to solution

hi

 

have you added the the required vhdl files or ngc? and modified the .pao file?

Deepa

View solution in original post

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Contributor
Contributor
6,582 Views
Registered: ‎08-04-2009

Re: Error NgdBuild 604 with a custom IP

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  Try to import the Custom IP once again .. If there are HDL errors it might show up while importing , as the error says " misspelling in ICAP_reboot "

 

 May be this helps

 Archu

 

 

 

 

Regards
Archu
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6,570 Views
Registered: ‎06-29-2009

Re: Error NgdBuild 604 with a custom IP

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Thanx for reply.   I tried that now and a few extra things (see my text I edited) but it doesn't help

 

I got an error though,  at the end when using the IP wizard (i always received that error)  :

 

ERROR:EDK - C:\DOCUMENTEN\STRES_III\Reference_design\sp601_bist\system.mhs line 445 - PARAMETER C_SPLIT has value 8 which does not fall in the range (1:C_SIZE_IN-1), specified in MPD
 

But that error does not appear later.

 

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Adventurer
Adventurer
8,205 Views
Registered: ‎08-19-2009

Re: Err. NgdBuild 604; custom IP; Tried many tricks on this forum

Jump to solution

hi

 

have you added the the required vhdl files or ngc? and modified the .pao file?

Deepa

View solution in original post

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6,556 Views
Registered: ‎06-29-2009

Re: Err. NgdBuild 604; custom IP; Tried many tricks on this forum

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Hi Deepa,

 

Great, thanx, It's ok now ...   it was indeed the PAO file that needed to be modified.

 

 

Serge

 

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