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Visitor
Visitor
8,856 Views
Registered: ‎11-07-2007

Error during synthesis with EDK9.2 and Multi Port Memory Controller

Hello,
I have a problem while synthesizing an EDK9.2 project including the multi-port memory controller v3.00.a. The controller is configured like this:
BEGIN mpmc
PARAMETER INSTANCE = MPMC3
PARAMETER HW_VER = 3.00.a
PARAMETER C_MEM_PARTNO = CUSTOM
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_PIM1_BASETYPE = 2
PARAMETER C_PIM2_BASETYPE = 3
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x07FFFFFF
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_CE_WIDTH = 2
PARAMETER C_MEM_CLK_WIDTH = 3
PARAMETER C_MEM_CS_N_WIDTH = 2
PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
PARAMETER C_SDMA_CTRL_HIGHADDR = 0x80007FFF
PARAMETER C_USE_STATIC_PHY = 1
PARAMETER C_NUM_PORTS = 3
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_REG_DIMM = 0
PARAMETER C_MEM_PART_DATA_DEPTH = 32
PARAMETER C_MEM_PART_NUM_COL_BITS = 10
PARAMETER C_MEM_PART_CAS_A_FMAX = 200
PARAMETER C_MEM_PART_TRAS = 40000
PARAMETER C_MEM_PART_TRASMAX = 70000000
PARAMETER C_MEM_PART_TRC = 55000
PARAMETER C_MEM_PART_TWR = 15000
PARAMETER C_MEM_PART_TRRD = 10000
PARAMETER C_MEM_PART_TRCD = 15000
PARAMETER C_MEM_PART_TREFI = 7800000
PARAMETER C_MEM_PART_TRFC = 75000
PARAMETER C_MEM_PART_TRP = 15000
PARAMETER C_MEM_PART_CAS_A = 2
BUS_INTERFACE SPLB0 = ppc405_0_iplb1
BUS_INTERFACE SPLB1 = ppc405_0_dplb1
BUS_INTERFACE SDMA_LL2 = hard_ethernet_mac_llink0
BUS_INTERFACE SDMA_CTRL2 = plb
PORT DDR_DQS = MPMC3_DDR_DQS
PORT DDR_DM = MPMC3_DDR_DM
PORT DDR_DQ = MPMC3_DDR_DQ
PORT DDR_Addr = MPMC3_DDR_Addr
PORT DDR_BankAddr = MPMC3_DDR_BankAddr
PORT DDR_WE_n = MPMC3_DDR_WE_n
PORT DDR_CAS_n = MPMC3_DDR_CAS_n
PORT DDR_RAS_n = MPMC3_DDR_RAS_n
PORT DDR_Clk_n = MPMC3_DDR_Clk_n
PORT DDR_Clk = MPMC3_DDR_Clk
PORT DDR_CS_n = MPMC3_DDR_CS_n
PORT MPMC_Rst = sys_bus_reset
PORT MPMC_Clk90 = MPMC3_SDRAM_CUSTOM_mpmc_clk_90_s
PORT MPMC_Clk0 = sys_clk_s
PORT SDMA2_Clk = temac_clk_s
PORT MPMC_Clk_Mem = dcm_ddr_fb
PORT DDR_CE = MPMC3_DDR_CE
PORT MPMC_DCM_PSEN = net_gnd
PORT SDMA2_Tx_IntOut = MPMC3_SDMA2_Tx_IntOut
PORT SDMA2_Rx_IntOut = MPMC3_SDMA2_Rx_IntOut
END

During synthesis (the EDK project is synthesized with ISE9.2), I get the following errors for each DDR datas and strobes:

ERROR:Xst:528 - Multi-source in Unit on signal <0>>
Sources are:
Primary input port <0>>
Output port IOBUF:IO of instance

ERROR:Xst:528 - Multi-source in Unit on signal <0>>
Sources are:
Primary input port <0>>
Output port IOBUF:IO of instance

Any ideas please ?

Thank you.
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Xilinx Employee
Xilinx Employee
8,850 Views
Registered: ‎08-06-2007

Hi,
 
Have you downloaded SP1?
I think it should be available now.
 
Göran
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Adventurer
Adventurer
8,846 Views
Registered: ‎11-07-2007

 I've got the same problem.  It complains about a multi-source for my DQ and DQS signals for the DDR SDRAM.  If you find a fix, please let me know.
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Visitor
Visitor
8,843 Views
Registered: ‎11-07-2007

Hi,
yes, SP1 is installed ...
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Visitor
Visitor
8,795 Views
Registered: ‎11-07-2007

the solution is the following:

go the "Ports" window in EDK.
the net name and the pin name must be the same. If not, a signal is created into the top level vhdl file and the pin is not directly connected to the memory controler ...
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