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Newbie abdous
Newbie
2,451 Views
Registered: ‎08-01-2012

Error in design with multiple BRAM controllers (v14.1)

Hi all,

I've successfully used EDK 13.4 with 128KB of onchip ram (multiple BRAM controller for data and instruction). But in 14.1 ISE shows error at bitgen process which is:

 

PhysDesignRules:368 - The signal <dcep_rxtx_i/microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_1a_BRAM_Addr<13>> is incomplete. The signal is not driven by any source pin in the design. 

 

 

 Also compare to 13.4 in "map" process, 14.1 shows these errors as a warnings.

Other strage issue is the edkBmmFile_bd.bmm file. One block ram in this file don't contain place information!

I think there is a bug in 14.1 bitgen. I've attached the bmm file.

 

 MHS for 13.4:

 

 

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 14.1 Build EDK_P.15xf # Sat Jul 28 13:15:44 2012 # Target Board: Custom # Family: spartan6 # Device: xc6slx150t # Package: fgg676 # Speed Grade: -3 # ############################################################################## PARAMETER VERSION = 2.1.0 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 PORT CLK = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT RS232_0_RX_pin = RS232_0_RX, DIR = I PORT RS232_0_TX_pin = RS232_0_TX, DIR = O PORT RS232_1_RX_pin = RS232_1_RX, DIR = I PORT RS232_1_TX_pin = RS232_1_TX, DIR = O BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_1_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_i_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_1_ilmb BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_i_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_1_ilmb BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_1_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_d_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_1_dlmb BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_d_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_1_dlmb BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_1_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block END BEGIN bram_block PARAMETER INSTANCE = microblaze_1_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block_1a BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN microblaze PARAMETER INSTANCE = microblaze_1 PARAMETER HW_VER = 8.20.b PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X00000000 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X00000000 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_1_ilmb BUS_INTERFACE DLMB = microblaze_1_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_1 BUS_INTERFACE DEBUG = microblaze_1_debug PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_96_0000MHz END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_1a BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 8.20.b PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X00000000 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X00000000 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_0_ilmb BUS_INTERFACE DLMB = microblaze_0_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_0 BUS_INTERFACE DEBUG = microblaze_0_debug PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_96_0000MHz END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.b PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_UART = 1 PARAMETER C_MB_DBG_PORTS = 2 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug BUS_INTERFACE MBDEBUG_1 = microblaze_1_debug PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT S_AXI_ACLK = clk_48_0000MHz END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 4.03.a PARAMETER C_CLKIN_FREQ = 100000000 PARAMETER C_CLKOUT0_FREQ = 96000000 PARAMETER C_CLKOUT0_GROUP = NONE PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT0_DUTY_CYCLE = 0.500000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT1_DUTY_CYCLE = 0.500000 PARAMETER C_CLKOUT1_FREQ = 48000000 PARAMETER C_CLKOUT1_GROUP = NONE PARAMETER C_CLKOUT1_PHASE = 0 PORT LOCKED = proc_sys_reset_0_Dcm_locked PORT CLKOUT0 = clk_96_0000MHz PORT RST = RESET PORT CLKIN = CLK PORT CLKOUT1 = clk_48_0000MHz END BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_0 PARAMETER HW_VER = 1.05.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn PORT INTERCONNECT_ACLK = clk_48_0000MHz END BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_1 PARAMETER HW_VER = 1.05.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn PORT INTERCONNECT_ACLK = clk_48_0000MHz END BEGIN axi_uartlite PARAMETER INSTANCE = RS232_0 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = 57600 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_48_0000MHz PORT RX = RS232_0_RX PORT TX = RS232_0_TX END BEGIN axi_uartlite PARAMETER INSTANCE = RS232_1 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = 57600 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_1 PORT S_AXI_ACLK = clk_48_0000MHz PORT RX = RS232_1_RX PORT TX = RS232_1_TX END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 3.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT Dcm_locked = proc_sys_reset_0_Dcm_locked PORT MB_Reset = proc_sys_reset_0_MB_Reset PORT Slowest_sync_clk = clk_48_0000MHz PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn PORT Ext_Reset_In = RESET PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET END 

 

MHS for 14.1 (some changes in HW core versions)

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 14.1 Build EDK_P.15xf # Sat Jul 28 13:15:44 2012 # Target Board: Custom # Family: spartan6 # Device: xc6slx150t # Package: fgg676 # Speed Grade: -3 # ############################################################################## PARAMETER VERSION = 2.1.0 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 PORT CLK = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT RS232_0_RX_pin = RS232_0_RX, DIR = I PORT RS232_0_TX_pin = RS232_0_TX, DIR = O PORT RS232_1_RX_pin = RS232_1_RX, DIR = I PORT RS232_1_TX_pin = RS232_1_TX, DIR = O BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_1_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_i_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_1_ilmb BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_i_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_1_ilmb BUS_INTERFACE BRAM_PORT = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_1_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_d_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_1_dlmb BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_1_d_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_1_dlmb BUS_INTERFACE BRAM_PORT = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_1_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block END BEGIN bram_block PARAMETER INSTANCE = microblaze_1_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_1_i_bram_ctrl_2_microblaze_1_bram_block_1a BUS_INTERFACE PORTB = microblaze_1_d_bram_ctrl_2_microblaze_1_bram_block_1a END BEGIN microblaze PARAMETER INSTANCE = microblaze_1 PARAMETER HW_VER = 8.30.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X00000000 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X00000000 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_1_ilmb BUS_INTERFACE DLMB = microblaze_1_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_1 BUS_INTERFACE DEBUG = microblaze_1_debug PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_96_0000MHz END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_96_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl_1 PARAMETER HW_VER = 3.00.b PARAMETER C_BASEADDR = 0x00010000 PARAMETER C_HIGHADDR = 0x0001ffff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_1a BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_1a END BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 8.30.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X00000000 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X00000000 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_0_ilmb BUS_INTERFACE DLMB = microblaze_0_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_0 BUS_INTERFACE DEBUG = microblaze_0_debug PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_96_0000MHz END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.b PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_UART = 1 PARAMETER C_MB_DBG_PORTS = 2 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug BUS_INTERFACE MBDEBUG_1 = microblaze_1_debug PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT S_AXI_ACLK = clk_48_0000MHz END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 4.03.a PARAMETER C_CLKIN_FREQ = 100000000 PARAMETER C_CLKOUT0_FREQ = 96000000 PARAMETER C_CLKOUT0_GROUP = NONE PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT0_DUTY_CYCLE = 0.500000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT1_DUTY_CYCLE = 0.500000 PARAMETER C_CLKOUT1_FREQ = 48000000 PARAMETER C_CLKOUT1_GROUP = NONE PARAMETER C_CLKOUT1_PHASE = 0 PORT LOCKED = proc_sys_reset_0_Dcm_locked PORT CLKOUT0 = clk_96_0000MHz PORT RST = RESET PORT CLKIN = CLK PORT CLKOUT1 = clk_48_0000MHz END BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_0 PARAMETER HW_VER = 1.06.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn PORT INTERCONNECT_ACLK = clk_48_0000MHz END BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_1 PARAMETER HW_VER = 1.06.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn PORT INTERCONNECT_ACLK = clk_48_0000MHz END BEGIN axi_uartlite PARAMETER INSTANCE = RS232_0 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = 57600 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_48_0000MHz PORT RX = RS232_0_RX PORT TX = RS232_0_TX END BEGIN axi_uartlite PARAMETER INSTANCE = RS232_1 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = 57600 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_1 PORT S_AXI_ACLK = clk_48_0000MHz PORT RX = RS232_1_RX PORT TX = RS232_1_TX END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 3.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT Dcm_locked = proc_sys_reset_0_Dcm_locked PORT MB_Reset = proc_sys_reset_0_MB_Reset PORT Slowest_sync_clk = clk_48_0000MHz PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn PORT Ext_Reset_In = RESET PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET END 

 

 

 

 

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1 Reply
Scholar austin
Scholar
2,448 Views
Registered: ‎02-27-2008

Re: Error in design with multiple BRAM controllers (v14.1)

a,

 

Generally, moving from an older version, to a newer version of the EDK redsults in many warnings and errors, and a result that doesn't work at all.  You have now discovered that.

 

It is not a bug:  it is the blocks that you used were all upgraded to the latest and greatest onces when it was rebuilt.  You need to say "no" whn asked if you want the newer versions.  Newer versions of the IP blocks are neither forward, nor backward compatible:  they often contain changes, new features, etc.

 

Beyond that, there may be other issues.  My rule is always to use one version from beginning to end, of a project/product.  I would take one of the development machines, and carefully documant everything, and put all the CD's etc. in a box with the machine, so that all future changes, etc. would get made ONLY with that environment.  Changing to a new version of the software was something I never did (unless it was unavoidable because it solved a major problem that could not be solved any other way).

 

The base system examples are built, and debugged for the demostration platforms they are offered with, and it is necessary to use these examples with the version they were built for.  These are only examples of what you can do.  When you build your own system for your application, you need to lock down everything, choose and document everything, and then make it all work (and place it under engineering change controls).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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