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hopsa
Observer
Observer
723 Views
Registered: ‎11-14-2014

Error in xparameters.h when using nonstandard IPI configuration

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I've discovered a bug in Vivado 2018.2 or SDK 2018.2, I'm not quite sure where in the flow the mistake happens.

Steps to reproduce:

  • open a project for a zynq ultrascale that includes the MPSOC IP block
  • in the mpsoc IP block configure the IPI master mapping so IPI 0 belongs to 'none' and IPI 7-10 belong to 'APU' (see the attached image)
  •  create bitstream, export hardware and import to SDK
  • Create a bsp for one of the a53 cores in the SDK

In the generated xparameters.h i find the following snippet:

#define  XPAR_XIPIPSU_NUM_INSTANCES  4U

/* Parameter definitions for peripheral psu_ipi_10 */
#define  XPAR_PSU_IPI_10_DEVICE_ID  0U
#define  XPAR_PSU_IPI_10_BASE_ADDRESS  0xFF370000U
#define  XPAR_PSU_IPI_10_BIT_MASK  0x08000000U
#define  XPAR_PSU_IPI_10_BUFFER_INDEX  6U
#define  XPAR_PSU_IPI_10_INT_ID  64U

/* Parameter definitions for peripheral psu_ipi_7 */
#define  XPAR_PSU_IPI_7_DEVICE_ID  1U
#define  XPAR_PSU_IPI_7_BASE_ADDRESS  0xFF340000U
#define  XPAR_PSU_IPI_7_BIT_MASK  0x01000000U
#define  XPAR_PSU_IPI_7_BUFFER_INDEX  3U
#define  XPAR_PSU_IPI_7_INT_ID  61U

/* Parameter definitions for peripheral psu_ipi_8 */
#define  XPAR_PSU_IPI_8_DEVICE_ID  2U
#define  XPAR_PSU_IPI_8_BASE_ADDRESS  0xFF350000U
#define  XPAR_PSU_IPI_8_BIT_MASK  0x02000000U
#define  XPAR_PSU_IPI_8_BUFFER_INDEX  4U
#define  XPAR_PSU_IPI_8_INT_ID  65U

/* Parameter definitions for peripheral psu_ipi_9 */
#define  XPAR_PSU_IPI_9_DEVICE_ID  3U
#define  XPAR_PSU_IPI_9_BASE_ADDRESS  0xFF360000U
#define  XPAR_PSU_IPI_9_BIT_MASK  0x04000000U
#define  XPAR_PSU_IPI_9_BUFFER_INDEX  5U
#define  XPAR_PSU_IPI_9_INT_ID  63U

 

The problem with that is the line "XPAR_PSU_IPI_8_INT_ID  65U". Interrupt number 65 is for IPI channel 1 which in my configuration belongs to the RPU. The correct value would be 62.

As a workaround I'm changing the interrupt number in the Ipi config before i do the XIpiPsu_CfgInitialize call.


This works fine for me, but It would be better if this got fixed in the toolchain.

ultrascalebug1.PNG
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ritakur
Xilinx Employee
Xilinx Employee
692 Views
Registered: ‎09-01-2014
This looks like a bug, 2018.3 is showing the same incorrect IRQ number.
I will report it to the engineer to get it fixed.

View solution in original post

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ritakur
Xilinx Employee
Xilinx Employee
693 Views
Registered: ‎09-01-2014
This looks like a bug, 2018.3 is showing the same incorrect IRQ number.
I will report it to the engineer to get it fixed.

View solution in original post

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