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bithuxiaoming
Observer
Observer
7,070 Views
Registered: ‎08-11-2008

FSL_M_CLk and FSL_S_CLK lost in EDK 11.3 when importing the IP.

I'm trying to use the ip windward to create a fsl ip without modifying any parameter and import it into the edk project,

however it report the FSL_M_CLk and FSL_S_CLK are lost, the pao is list as below: will anyone can help me on

this problem? Thanks for your help.

 

##############################################################################
## Filename:          E:\FPGA\ISEAPPs\ASIA2010\fsl\pcores/f1_v1_00_a/data/f1_v2_1_0.mpd
## Description:       Microprocessor Peripheral Description
## Date:              Thu Aug 19 22:05:51 2010 (by Create and Import Peripheral Wizard)
##############################################################################

BEGIN f1

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
## Bus Interfaces
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER

## Peripheral ports
PORT FSL_Clk = "", DIR=I, SIGIS=Clk, BUS=MFSL:SFSL
PORT FSL_Rst = OPB_Rst, DIR=I, BUS=MFSL:SFSL
PORT FSL_S_Clk = FSL_S_Clk, DIR=O, SIGIS=Clk, BUS=SFSL
PORT FSL_S_Read = FSL_S_Read, DIR=O, BUS=SFSL
PORT FSL_S_Data = FSL_S_Data, DIR=I, VEC=[0:31], BUS=SFSL
PORT FSL_S_Control = FSL_S_Control, DIR=I, BUS=SFSL
PORT FSL_S_Exists = FSL_S_Exists, DIR=I, BUS=SFSL
PORT FSL_M_Clk = FSL_M_Clk, DIR=O, SIGIS=Clk, BUS=MFSL
PORT FSL_M_Write = FSL_M_Write, DIR=O, BUS=MFSL
PORT FSL_M_Data = FSL_M_Data, DIR=O, VEC=[0:31], BUS=MFSL
PORT FSL_M_Control = FSL_M_Control, DIR=O, BUS=MFSL
PORT FSL_M_Full = FSL_M_Full, DIR=I, BUS=MFSL

END

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7 Replies
htsvn
Xilinx Employee
Xilinx Employee
7,066 Views
Registered: ‎08-02-2007

Hi,

 

Looks like CIP was not able to automatically map FSL_M_CLK and FSL_S_CLK.

 

So we need to modify the HDL or manually select our ports.

 

Thnx

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bithuxiaoming
Observer
Observer
7,050 Views
Registered: ‎08-11-2008

So will you please tell me how to correct the hdl file or where can I manually select the ports. Because in the CIP

when it report the error it halts.

Even the CIP report error, and it seems that the IP is import into the project. and the port is connecting as the picture,

however, when I test the FSL IP as the default vhdl, it seem the accumulater doesn't work correctly.

 

Thanks.

FSL Import.JPG
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htsvn
Xilinx Employee
Xilinx Employee
6,978 Views
Registered: ‎08-02-2007

Hi,

 

Are you using the FSL in Synchronous mode or Asynchronous mode?

 

FSL_CLK is the input clock to the FSL bus when used in the synchronous FIFO mode (C_ASYNC_CLKS = 0). The
FSL_Clk is used as the clock for both the master and slave interfaces

 

FSL_M_CLK  port provides the input clock to the master interface of the FSL bus when used in the asynchronous FIFO mode
(C_ASYNC_CLKS = 1).

 

FSL_S_CLK port provides the input clock to the slave interface on the FSL bus when used in the asynchronous FIFO mode (C_ASYNC_CLKS = 1). 

 

If you are using Asynchronous mode, let us know the procedure of importing this FSL.

 

Thnx

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arwa
Contributor
Contributor
6,708 Views
Registered: ‎02-18-2008

I'm having the same problem trying to import an FSL peripheral in 12.3 :

 

"The Wizard was not able to automatically map all bus interface ports for MFSL. Please manually select your ports or modify your HDL file."  It can't find the FSL_M_Clk. Same with the FLS_S_Clk. I've checked the HDL, the ports exist!

 

Where do I have the option of specifying whether the FIFOs work in synchronous or asynchronous modes, if that is the problem? There was no such option when creating the FSL based peripheral...

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htsvn
Xilinx Employee
Xilinx Employee
6,699 Views
Registered: ‎08-02-2007

Hi,

 

Importing this peripheral into EDK system:-

 

 

1, Go to Hardware => Configure Co processor

 

 

2, You will be able to see the created peripheral

 

 

3, Select the peripheral and use the Add button to include it into the system. Once this is done, Click OK.

 

 

4, Once this is done, you will be able to see the peripheral being connected to FSL bus.

 

 

 Thnx

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xiaofeip_dup
Xilinx Employee
Xilinx Employee
6,578 Views
Registered: ‎08-07-2007

Just want to clarify one thing, you don't need to import a custom peripheral after creating one. To use the core in XPS, just put it into pcores directory after creating it will be sufficient.

 

The Import Wizard is helpful if you have changed the HDL code of  your custom peripheral and you want the Wizard to update the MPD, PAO, etc. supporting files automatically. You don't have to use it if you know how to manually update those supporting files.

 

-Felix

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arwa
Contributor
Contributor
6,377 Views
Registered: ‎02-18-2008

Actually, the problem seems to have been a mistake in the direction of the clocks FSL_M_Clk and FSL_S_Clk when the Create or Import Peripheral wizard is used. In Xilinx 12.3 both these clocks are output ports when they should have been input ports - someone else mentioned this in the forums in some post that I can't locate now. It worked when I changed the direction of the ports.

 

This has been fixed in version 12.4 of EDK.

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