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Visitor
Visitor
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Registered: ‎10-19-2020

Getting Started with Xilinx ISE 14.7 simulation

Hi everyone,

I want to calculate the processing time of a digital circuit using simulation, and I have downloaded the Xilinx ISE 14.7 for Windows 10. However, there are so many supporting documents for ISE 14.7 that I am not able to understand how to start with it. Would someone please help me to get started with the Xilinx tool?

Also, since FPGAs usually optimize the processing time of the circuit, is it possible to perform the timing analysis using the Xilinx simulation? For example, is it possible to calculate the processing time of a digital circuit like a Mux decoder or an n-input logic gate, etc.?

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Teacher
Teacher
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Registered: ‎07-09-2009

what do you mean by processing time ?
that sounds more like a software question,

FPGAs have a propagation time, along with the associated set up and hold times.

https://en.wikipedia.org/wiki/Propagation_delay

Simulation is NOT the way to find propagation time,
not least , the normal test bench assumes "1 delta" , next to zero propagation delay,


Timing in FPGAs is dependent upon how the FPGA is synthesised, which you do after you have proven the design in simulation,

Synthesis works on your code, and then optimises it in various ways, to meet your constraints, including timing,
these constraints are defined in ISE in the UCF files you write.

The timing you achieve, is reported in the timing file generated by the tools. I think thats the .twr file,

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Visitor
Visitor
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Registered: ‎10-19-2020

Thank you for your response @drjohnsmith.

The processing time means the time taken by a digital circuit to reflect the change in output after applying input. For example, the time required by a 2x1 mux to provide output=D0 for select line =0 or to provide output=D1 for select line =1.

I am designing an asynchronous circuit with handshaking signals and I want to compare the time required to reflect the change in output after applying input for both synchronous and asynchronous designs. Is it possible to achieve this by analyzing the .twr files for both designs?

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Teacher
Teacher
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Registered: ‎07-09-2009

That's called propergation time in digital electronics. 

Tphl and Tplh in an io pin.

Simulation will put these times at 1 delta, normally about 1ps , so no use for what u want. 

U need to look up timming report ..

 

 

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Visitor
Visitor
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Registered: ‎10-19-2020

Thank you for your reply.

Can we generate the timing report using Xilinx or I need to look for some other software to calculate the timing constraints for a digital circuit?

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Teacher
Teacher
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Registered: ‎07-09-2009

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Visitor
Visitor
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Registered: ‎10-19-2020

Thank you so much, I will check them out.

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Visitor
Visitor
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Registered: ‎10-19-2020

Hi @drjohnsmith,

You have shared the link https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/timingan/timingan.htm#html/ta_hidr_twx_report_viewer.htm  which provides a course on timing analyzer. The representation is user-friendly, as the left pane is showing all the contents covered for the course and it can be accessed by clicking the topic. I was wondering whether a similar course is available for the Xilinx ISE basics and how to access it. I have tried to use the support link given on the Xilinx website, but that link is providing pdfs. I would be grateful if you can guide me on how to find any ISE course similar to the timing analyzer course representation provided in the above link. 

 

 
 

 

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Teacher
Teacher
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Registered: ‎07-09-2009

I have no connection to xilinx, and its a long time since I have done ISE stuff

Sorry, google is your friend
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Visitor
Visitor
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Registered: ‎10-19-2020

Ok no problem, Thank you for your reply.

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