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Registered: ‎09-10-2007

How can I reduce the required time for generating bitstream?

Hi,
please help me with this problem,
I have written a user peripheral in Xilinx 8.2 , and in this peripheral I have used GCM component that I had written before,
in the user_logic.vhd I have 2 process one for writing into input ports of GCM component and another for reading from output ports.
Now my problem is when I only have the process for writing, it takes at most 15 minutes for the bitstream generation, and also when I have another process for reading if I don't add the lines for reading output ports of GCM it's ok too. But when I add those lines, the time of generating bitstream increases very much, up to 6 hours,
please say me if there are some methods that help me to save the bitstream of my GCM component one time and after that just use it and don't make it every time that I want to generate
it? Or do you have any advices that help me reducing the time of making bitstream,
I  have enclosed my code of User_logic if you want take a look at it, also the line of causing problem is like
when 4 => slv_reg5(0 to 31) <= CipherText_TAG(127 Downto 96);
                   

thanks,
M. Hajiaghayi
 ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_DWIDTH                       : integer              := 32;
    C_NUM_CE                       : integer              := 10;
    C_IP_INTR_NUM                  : integer              := 1
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_IP_INTR_NUM-1);
    Bus2IP_Data                    : in  std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_DWIDTH-1);
    IP2Bus_Ack                     : out std_logic;
    IP2Bus_Retry                   : out std_logic;
    IP2Bus_Error                   : out std_logic;
    IP2Bus_ToutSup                 : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic
 component  GCM
  port(
     
       clk       : in std_logic;
      reset     : in std_logic;
      mode      : in std_logic; -- to select encryption or decryption
      load_data      : in std_logic; -- to load the input and keys.has to
      load_AAD      : in std_logic;
      load_key   : in std_logic;
      PlainText_AAD_KEY_IV  : in std_logic_vector(127 downto 0);
      CipherText_TAG    : out std_logic_vector(127 downto 0);
      LenA      : in std_logic_vector(63 downto 0);
      LenC      : in std_logic_vector(63 downto 0);
      iv_load      : in std_logic;
      TAG_rdy      : out std_logic;
      cipher_rdy :  out std_logic
     );
    
end component;
  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg4                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg5                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg6                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg7                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg8                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg9                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg_write_select           : std_logic_vector(0 to 9);
  signal slv_reg_read_select            : std_logic_vector(0 to 9);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

  ------------------------------------------
  -- Signals for user logic interrupt example
  ------------------------------------------
  signal interrupt                      : std_logic_vector(0 to C_IP_INTR_NUM-1);
  signal    clk       :std_logic:='0';
  signal    reset     :std_logic:='0';
  signal    mode      :std_logic:='1'; -- to select encryption or decryption
  signal load_data      :std_logic:='0'; -- to load the input and keys.has to
  signal load_AAD      : std_logic:='0';
  signal load_key   : std_logic:='0';
  signal    PlainText_AAD_KEY_IV  : std_logic_vector(127 downto 0);
  signal    CipherText_TAG    : std_logic_vector(127 downto 0);
  signal    LenA      : std_logic_vector(63 downto 0):=X"0000000000000000";
  signal    LenC      : std_logic_vector(63 downto 0):=X"0000000000000080";
  signal    iv_load      :  std_logic:='0';
  signal    TAG_rdy      :  std_logic:='0';
  signal    cipher_rdy :  std_logic:='0';
  signal state     : std_logic_vector(0 to 3);
 
begin

  --USER logic implementation added here
aGCM_unit: GCM
       port map(
                  clk      => clk,
                  reset    => reset,
                  mode     => mode,
                  load_data     => load_data,
                  load_AAD =>  load_AAD,
                  load_key  => load_key,
                  PlainText_AAD_KEY_IV    => PlainText_AAD_KEY_IV,
                  CipherText_TAG => CipherText_TAG,
                  LenA => X"0000000000000000",
                  LenC =>X"0000000000000080",
                  iv_load => iv_load ,
                  TAG_rdy     => TAG_rdy,
                  cipher_rdy => cipher_rdy
                ); 
 clk <= Bus2IP_Clk;
 reset <= Bus2IP_Reset;              
  slv_reg_write_select <= Bus2IP_WrCE(0 to 9);
  slv_reg_read_select  <= Bus2IP_RdCE(0 to 9);
  slv_write_ack        <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or       Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9);
  slv_read_ack         <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9);

  -- implement slave model register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
     --   slv_reg4 <= (others => '0');
     --   slv_reg5 <= (others => '0');
     --   slv_reg6 <= (others => '0');
     --   slv_reg7 <= (others => '0');
    --   slv_reg8 <= (others => '0');
     --   slv_reg9 <= (others => '0');
      else
        case slv_reg_write_select is
          when "1000000000" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0100000000" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0010000000" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0001000000" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model register read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9 ) is
  begin

    case slv_reg_read_select is
      when "1000000000" => slv_ip2bus_data <= slv_reg0;
      when "0100000000" => slv_ip2bus_data <= slv_reg1;
      when "0010000000" => slv_ip2bus_data <= slv_reg2;
      when "0001000000" => slv_ip2bus_data <= slv_reg3;
      when "0000100000" => slv_ip2bus_data <= slv_reg4;
      when "0000010000" => slv_ip2bus_data <= slv_reg5;
      when "0000001000" => slv_ip2bus_data <= slv_reg6;
      when "0000000100" => slv_ip2bus_data <= slv_reg7;
      when "0000000010" => slv_ip2bus_data <= slv_reg8;
      when "0000000001" => slv_ip2bus_data <= slv_reg9;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

   IP2Bus_IntrEvent <= interrupt;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= slv_ip2bus_data;

  IP2Bus_Ack         <= slv_write_ack or slv_read_ack;
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';
ACTIVATE_LOAD : process(Bus2IP_Clk) is
     
     variable   counter      : integer :=0;
     variable   cnt1      : integer :=0;
      variable   flag      : std_logic:='0';
     variable   flag1      : std_logic:='0';
      begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
      if ( Bus2IP_Reset = '1' ) then
          --slv_reg9(0 to 31) <= X"00000001";
          load_AAD  <= '0';
           load_key  <= '0';
           state <="0000";
           counter  := 5;
            flag := '0';
            flag1 :='0';
        else
            case state is
                when "0000" =>
                    flag:= '0';
                    flag1:= '0';
                   
                    if (slv_reg_write_select="1000000000") then
                        if (counter = 5) then
                            counter := 4;
                        else     
                          case counter is                               
                                when 4 => PlainText_AAD_KEY_IV(127 Downto 96) <= slv_reg0(0 to 31);
                                when 3 => PlainText_AAD_KEY_IV(95 Downto 64) <= slv_reg0(0 to 31);
                                when 2 => PlainText_AAD_KEY_IV(63 Downto 32) <= slv_reg0(0 to 31);
                                when 1 => PlainText_AAD_KEY_IV(31 Downto 0) <= slv_reg0(0 to 31);
                                when others => counter := counter ;
                            end case;
                           
                            if (counter=1 ) then
                                state<="0001" ;
                                load_key<='1';
                                counter:=4;
                            else
                                counter:=counter-1;
                            end if;
                        end if;   
                    end if;   
     when "0001" =>
                    load_key<='0';
                    if (slv_reg_write_select="0100000000") then
                       
                        if (counter = 0) then
                                if (cnt1 = 300) then
                                    iv_load <= '1';
                                    state<="0010" ;                     
                                    counter:=5;
                                    cnt1:=0;
                                else
                                    cnt1:= cnt1+1;
                                end if;
                         
                 
                        elsif (counter = 4)then
                           counter := 3;
                       
                        else
                        case counter is                               
                                when 3 => PlainText_AAD_KEY_IV(95 Downto 64) <= slv_reg1(0 to 31);
                                when 2 => PlainText_AAD_KEY_IV(63 Downto 32) <= slv_reg1(0 to 31);
                                when 1 => PlainText_AAD_KEY_IV(31 Downto 0) <= slv_reg1(0 to 31);
                                when others => counter := counter ;
                       end case;
                            counter:=counter-1;
              
                       end if;   
                end if;
         when "0010"  =>
         
                 iv_load <= '0';
                 if (slv_reg_write_select="0010000000") then
                  
               if (counter = 0) then
                 if (cnt1 = 300) then
                      load_AAD<='1';
                      counter:=5;
                      flag := '1';
                      flag1:= '0';
                      cnt1 := 0;
                   else
                     cnt1:= cnt1+1;
                  end if;
                          
                 elsif (counter = 5 and flag = '0')then
                         load_AAD <= '0';
                       PlainText_AAD_KEY_IV <=X"00000000000000000000000000000000";
                       counter := 4;
                 else
                    if (counter = 5) then
                          load_AAD<='0';
                           PlainText_AAD_KEY_IV <=X"00000000000000000000000000000000";
                      counter := 4;                 
                    end if;      
                  
                    case counter is                               
                                when 4 => PlainText_AAD_KEY_IV(127 Downto 96) <= slv_reg2(0 to 31);
                                when 3 => PlainText_AAD_KEY_IV(95 Downto 64) <= slv_reg2(0 to 31);
                                when 2 => PlainText_AAD_KEY_IV(63 Downto 32) <= slv_reg2(0 to 31);
                                when 1 => PlainText_AAD_KEY_IV(31 Downto 0) <= slv_reg2(0 to 31);
                                when others => counter := counter ;
                    end case;
                    counter:=counter-1;
                   
                end if;
                elsif (slv_reg_write_select="0001000000") then
                   
                        load_AAD<='0';
                   
                        if (counter = 0) then
                          if (cnt1 = 400) then
                              load_data<='1';
                              counter:=5;
                              flag1 :='1';
                              flag := '0';
                              cnt1 := 0;
                         
                          else
                              cnt1:= cnt1+1;
                          end if;
                        elsif (counter = 5 and flag1 ='0')then
                                    PlainText_AAD_KEY_IV <=X"00000000000000000000000000000000";
                                    counter := 4;
                                    load_data<='0';
                        else
                             if (counter = 5) then
                                    load_data <= '0';
                                    PlainText_AAD_KEY_IV <=X"00000000000000000000000000000000";
                                  counter := 4;
                             end if;      
                            case counter is                               
                                        when 4 => PlainText_AAD_KEY_IV(127 Downto 96) <= slv_reg3(0 to 31);
                                        --slv_reg4 <= X"AAD00000";
                                        when 3 =>PlainText_AAD_KEY_IV(95 Downto 64) <= slv_reg3(0 to 31);
                                        when 2 => PlainText_AAD_KEY_IV(63 Downto 32) <= slv_reg3(0 to 31);
                                        when 1 => PlainText_AAD_KEY_IV(31 Downto 0) <= slv_reg3(0 to 31);
                                        when others => counter := counter ;
                            end case;
                            counter:=counter-1;
                     end if;
                elsif (slv_reg_write_select="0000000010") then
                   load_data<='0';
                    load_AAD<='0';
                    iv_load <= '0';                                  
                    load_key <= '0';                                  
                    state<="0000" ;
                    counter:=5;
                end if;                                       
                when others =>
           
                                load_data<='0';
                                load_AAD<='0';
                                iv_load <= '0';                                  
                                load_key <= '0';                                  
                                state<="0000" ;
                        end case;
      end if;
end if;                    
end process  ACTIVATE_LOAD;

WRITE_DATA : process( Bus2IP_Clk, cipher_rdy ) is
  variable counter      : integer := 4;
  variable fl:    std_logic:= '0';        
  variable fl1 :    std_logic:= '1';
   

  begin
  if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
     if ( Bus2IP_Reset = '1' ) then
             counter := 4;
             slv_reg4 <= X"00000000";
     elsif(    cipher_rdy = '1' or fl = '1') then
          slv_reg4 <= X"00000000";
             fl :='1';
               case counter is                               
                    when 4 => slv_reg5(0 to 31) <= CipherText_TAG(127 Downto 96);
                      slv_reg4 <= X"00000001";
                    when 3 => slv_reg6(0 to 31) <= CipherText_TAG(95 Downto 64);
                    slv_reg4 <= X"00000001";
                    when 2 => slv_reg7(0 to 31) <= CipherText_TAG(63 Downto 32);
                    slv_reg4 <= X"00000001";
                    when 1 => slv_reg9(0 to 31) <= CipherText_TAG(31 Downto 0);
                    slv_reg4 <= X"00000001";
                    when others => counter := counter ;
                    slv_reg4 <= X"00000000";
                end case;
               if (counter = 1) then
                fl := '0';
                  counter := 4;
               else
                    counter := (counter -1);
               end if;
         elsif (Tag_rdy = '1' ) then
          if (fl1 = '1') then  
             case counter is                               
                    when 4 => slv_reg5(0 to 31) <= CipherText_TAG(127 Downto 96);
                      slv_reg4 <= X"00000001";
                    when 3 => slv_reg6(0 to 31) <= CipherText_TAG(95 Downto 64);
                    slv_reg4 <= X"00000001";
                    when 2 => slv_reg7(0 to 31) <= CipherText_TAG(63 Downto 32);
                    slv_reg4 <= X"00000001";
                    when 1 => slv_reg9(0 to 31) <= CipherText_TAG(31 Downto 0);
                    slv_reg4 <= X"00000001";
                    when others => counter := counter ;
                    slv_reg4 <= X"00000000";
                end case;
                   if (counter = 1) then
                      counter := 4;
                      flag1 := '0';
                   else
                        counter := (counter -1);
                  end if; 
            end if;         

      end if;
    end if;           
end process WRITE_DATA;
end IMP;

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Registered: ‎09-16-2007

Take a step back and think about what you need.  Maybe the best solution is to make your EDK design a slave to ISE and do everything inside ISE.  Then just write and read to registers.   You need to simulate alone with out the PPC junk getting in the way.

Not sure how long your code need to take but maybe IP2Bus_ToutSup signal needs to be asserted to prevent a timeout. If your code take longer than 8 clock cycles you need this.  Although I feels like its 6.

Cheers,
Bill Tomb
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