07-05-2017 09:29 AM
I want to have individually addressable IP blocks inside a higher level IP block. I have created a simple example so that I can explain my design.
The axiregister components are simple registers which store the last data value written to them over the axi lite interface. I have then used the Create and Package New IP tool to package this as an IP block (called double_reg). This block was then instantiated in a top level design:
If I set the address of each of the axiregisters inside the double_reg IP, using the address editor, then I can successfully write to both axiregisters.
I presume that this wouldn't work if I instantiate multiple instances of the double_reg IP (as I would have multiple blocks with the same hard coded addresses). To get round this problem I would like to set the addresses of the internal axiregister blocks from the top level design.
The Create and Package New IP tool contains an Addressing and Memory tab which seems to provide the functionality I'm looking for but I cannot find any useful information on line explaining how to use it.
07-07-2017 11:51 PM
>> I presume that this wouldn't work if I instantiate multiple instances of the double_reg IP (
Not sure why you presume this. Did you try it to see that it didn't work? One possibility is that the address editor would drill down the packaged ip and find all sub-blocks which need an address assigned. At least this is how it works for hierarchical block designs in BD editor.
If that actually doesn't work, the solution might be to declare the address space needs of the complete block just like you would for any regular IP during packaging ie how many ranges, whether they're memory or register etc so that they can be cumulatively enumerated during address assignment. It is actually disappointing that the package creation flow can't figure this out itself. It actually has all the information it needs to populate the addressing & memory tab.