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Voyager
Voyager
6,693 Views
Registered: ‎07-28-2008

How is EDK timing group saved?

I have a ISE top-level design with embedded EDK system.

 

I have been looking for net name of generated system clock inside the EDK:system. I know I can use planAhead synthesis result to find it.

 

But in ISE, I found in technology viewer some TIMEGRP name definitions.

 

It seems I can just use those TIMGRP name for my constraints. But for my curiosity, can someone please comment where are those timing group name defined in the first place? Are they generated automatically by EDK magic and kept in some magic file?

 

Also, in ISE 13.3+ is there a method to read net name from synthesized results instead of going for planAhead?

 

Thanks,

 

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Scholar
Scholar
6,676 Views
Registered: ‎06-14-2012

As you create the embedded system, few of the constraints are automaticallydefined based on the board and the system that you have configured. This can be found in system.ucf file under data folder of your xps project.

 

 

forums.bmp
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Scholar
Scholar
6,672 Views
Registered: ‎09-05-2011

Hi, 

 

You can check the .ncf files within the implementation folder. The Netlist Constraints File (NCF) is typically generated by a synthesis program. If constraints in UCF and NCF overlaps, UCF overrides NCF. 

 

Regards,

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Voyager
Voyager
6,663 Views
Registered: ‎07-28-2008

Thanks a lot for sharing your knowledge.

I've gone through all .ncf files in my design, there is no TIMEGRP for the name I was looking for.

After MAP, I can find TIMEGRP definitions in .bld, .pcf, .twr, and .twx files; I understood none of them are design entry files.

 

According to UG625: .pcf takes entry from:

  • attribute assigned in HDL
  • ucf
  • ncf
  • ngd (Logical constraints)

So the .ngd is my best guess or it's something else undocumented.

 

Bottom line for me, I got net name by using PlanAhead; and can use those TIMEGRP name from .pcf file to define my constraints. Although I am not very comfortable of doing things without knowing the logic behind, it seems working OK.

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Xilinx Employee
Xilinx Employee
6,660 Views
Registered: ‎08-02-2007

Hi,

 

ngd is used to define constraints. You can use the procedure documented in this link to create constraints using constraints editor.

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/Specify-user-constraints-UCF-for-Xilinx-Platform-Studio-custom/m-p/344667#M27903

 

--HS

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Scholar
Scholar
6,656 Views
Registered: ‎06-14-2012

Can you share your timegroup constraints? That will give a hint of where these constraints are coming from.

 

Back annotating from pcf is not a very good approach.

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Voyager
Voyager
6,646 Views
Registered: ‎07-28-2008

//! ***************************
// Written by: Map
//! ***************************
TIMEGRP Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 = BEL ... TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 200MHz HIGH 50% TS_Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 = PERIOD TIMEGRP "Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_sys_clk_pin * 0.5 HIGH 50%;
################## another clock
TS_ClockGen_inst_inst_Gen_200MHz_clkout0 = PEROID TIMEGRP
"ClockGen_inst_inst_Gen_200MHz_clkout0" TS_iClk300M_p / 0.64 HIGH 50%;
TS_Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_0 = PERIOD TIMEGRP "Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_0" TS_ClockGen_inst_inst_Gen_200MHz_clkout0 / 0.5 HIGH 50%;

################## another clock
TS_ClockGen_inst_inst_Gen_200MHz_clkout0_0 = PERIOD TIMEGRP
"ClockGen_inst_inst_Gen_200MHz_clkout0_0" TS_iClk300M_n / 0.64 HIGH 50%
TS_Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_1 = PERIOD TIMEGRP "Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_1" TS_ClockGen_inst_inst_Gen_200MHz_clkout0_0 / 0.5 HIGH 50%;
################## another clock
TS_ClockGen_inst_inst_Gen_200MHz_clkout0_1 = PERIOD TIMEGRP
"ClockGen_inst_inst_Gen_200MHz_clkout0_1" TS_sys_clk_f0 / 0.64 HIGH 50%
TS_Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_2 = PERIOD TIMEGRP "Inst_system_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0_2" TS_ClockGen_inst_inst_Gen_200MHz_clkout0_1 / 0.5 HIGH 50%;

My design hierarchy is: ISE top, a system embedded; clock to system (100MHz) is driven by a generated clock 200MHz from logic part. Logic part talks to System through GPIO ports, I assume GPIO peripheral internally has asynchronous settling logic.

 

So, if I don't assign TIG, DATAPATHONLY or Asynchronous data delay. Timing analyzer assumes synchrnous data path between 200MHz and 100MHz domain and report violation.

 

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Xilinx Employee
Xilinx Employee
6,624 Views
Registered: ‎08-02-2007

Hi,

 

The clocks derived from clock generator will have the constraints derived automatically. The only assumption here is that there is a period constraint on the input of clock generator. If you have a cross clock domain path(source and destination driven by a different clock), then you might want to either apply a false path(TIG) or Datapathonly constraint.

 

In this case too, you should be providing the constraints in UCF and be using Constraints Editor.

 

--HS

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Scholar
Scholar
6,616 Views
Registered: ‎06-14-2012

Yes these are geing generated by clock generator instance in your design. This constraints are being added based on your configuration for your system. These constraints are necessary unless you decide not to use them for your analysis.

 

 

 

 

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