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Visitor arabidze
Visitor
3,477 Views
Registered: ‎11-22-2013

How to connect MicroBlaze and VHDL module with AXI GPIO?

Hi!

 

I thought it should be easy enough to connect the MicroBlaze processor with the VHDL module, and make them talk to each other. But, here is the problem...

 

For the MicroBlaze embedded processor, I've got something like this in the main VHDL module, and I map axi_gpio to a signal:

 

signal axi_gpio_ch0  : std_logic_vector(31 downto 0);

 

Inst_mBlaze: mBlaze
    PORT MAP(
        axi_gpio_0_GPIO_IO_pin  => axi_gpio_ch0,
        ........
    );

 

Now, axi_gpio_0_GPIO_IO_pin has to be a buffer (OBUF in my case, as I define it as the input to mBlaze)..? so I have to write something like:

 

OBUF_Inst_ch1: OBUF
    port map(
        O => O,
         I => I
    ) ;

 

 

Can I connect OBUF to mBlaze? How can I connect and use axi_gpio_0_GPIO_IO_pin nternaly, without connecting to the FPGA pins.. is this possible?

 

Thanks,

Giorgi.

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2 Replies
Scholar sampatd
Scholar
3,474 Views
Registered: ‎09-05-2011

Re: How to connect MicroBlaze and VHDL module with AXI GPIO?

My advice - Have an AXI wrapper around your custom VHDL module and connect it to the processor's bus.

You might want to refer to chapter 6 of
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/edk_ctt.pdf

also,

the following AR will be helpful:
http://www.xilinx.com/support/answers/37425.htm
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Scholar stephenm
Scholar
3,453 Views
Registered: ‎05-06-2012

Re: How to connect MicroBlaze and VHDL module with AXI GPIO?

Look like you have an embedded submodule and connect this to your custom HDL code. However, your gpio has an Ovid on it.

This is expected, the tools will add output buffers on all external ports. You can disable this by adding the buffer_type=none to this port in EDK, or just delete this from your HDL wrapper
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