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Explorer
Explorer
6,763 Views
Registered: ‎06-22-2011

How to implement timeout for axi dma ip?

Hi all,

 

I want to use the axi dma ip with sg in my design. According to the product guide, for s2mm, a descriptor won't complete until all the data has been received. How to finish the descriptor if no data is received for a given period?

As I know, if the data source assert tlast, the descriptor will be forced to finish. Maybe I can monitor the data transfer outside of the IP and assert tlast accordingly. But how can I find the start of the processing of a descriptor?

 

best regards

 

Xiang Chao

 

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Xilinx Employee
Xilinx Employee
6,299 Views
Registered: ‎08-02-2011

Re: How to implement timeout for axi dma ip?

Hello,

 

Yeah, toggling tlast is probably going to be the best way to do this and software can read the BD status register to find out how many bytes were actually transferred.

 

But how can I find the start of the processing of a descriptor?

Depends on how you are using the core. Is it possible to set BDs to guarantee that their 'length' setting is greater than or equal to the incoming packet size? In that case, tlast will always delineate BDs. 

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