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Registered: ‎10-06-2009

How to link multiple modules to create IP

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As we link multiple modules files by adding differnet source files in xilinx ISE, ISE creates hiearchy itself for these modules as these modules are used and developed.But in EDK while creating IP, i have multiple modules checked and simulated on modelsim.Now i have to use it as IP.Modules names say a, b, and top level module as c.Now when i create IP on EDK ,i get user_logic file, i have to add code for top level module in it to interface, but question where i should add my sub modules a and b??? Should i add it in user_logic or is there any facility to add these source files separately in EDK while cretaing IP as we do in ISE?Kindly let me know.

 

 

nasim

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pavithra
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Registered: ‎10-25-2009
Hi u copy all URI vhdl files including toplevel module in the hdl->vhdl folder. use toplevel module as a component in user_logic.vhd file. Add the paths of submodules in .pao file. adding modules shohld be in heirachical means toplevel module should be in last. then import modified ip .

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pavithra
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Adventurer
4,492 Views
Registered: ‎10-25-2009
Hi u copy all URI vhdl files including toplevel module in the hdl->vhdl folder. use toplevel module as a component in user_logic.vhd file. Add the paths of submodules in .pao file. adding modules shohld be in heirachical means toplevel module should be in last. then import modified ip .

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pavithra
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Registered: ‎10-25-2009
Hi u copy all  vhdl files including toplevel module in the hdl->vhdl folder. use toplevel module as a component in user_logic.vhd file. Add the paths of submodules in .pao file. adding modules shohld be in heirachical means toplevel module should be in last. then import modified ip .
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3,638 Views
Registered: ‎10-06-2009
thanx for ur valuable suggestion.
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