I need your help

[dongtrungthao]

I use "creat and import peripheral" in EDK to creat opb_74 , then i use Project Navigator to edit user_logic.vhd . It don't have any error , but when I import it in my project , select1,2,3 (input) Loc with 3 buttons and output(0 to 15) Loc with 16 leds on my board  --> download to my board -->but when i push button , there aren't any leds light . Plz show me how i can use input (select1 ,2 ,3) . Because i see that " output is good , with this command output_1_1 <= "00001000"; one of 16 leds lighted when download finished but push button , nothing happen .PLZ HELP ME , THANK YOU
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 1;
C_IP_INTR_NUM : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
selectled1 :in std_logic;
selectled2 :in std_logic;
selectled3 :in std_logic;
output : out std_logic_vector (0 to 15);

-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic
signal selectled_a :std_logic;
signal selectled_b :std_logic;
signal selectled_c :std_logic;
signal output_1_1 : std_logic_vector(0 to 7);
signal output_1_2 : std_logic_vector(0 to 7);


------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 0);
signal slv_reg_read_select : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;

------------------------------------------
-- Signals for user logic interrupt example
------------------------------------------
signal interrupt : std_logic_vector(0 to C_IP_INTR_NUM-1);

begin

output(0 to 7) <= output_1_1;
output(8 to 15) <= output_1_2;
selectled_a <= selectled1;
selectled_b <= selectled2;
selectled_c <= selectled3;



--USER logic implementation added here
START : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
output_1_1 <= (others => '0');
output_1_2 <= (others => '0');
else
output_1_1 <= "00001000";
if selectled_a = '1' then
output_1_1 <= "00000001";
if selectled_b = '1' then
output_1_1 <= "00000010";
if selectled_c = '1' then
output_1_1 <= "00000100";
end if;
end if;
end if;
end if;
end if;
end process START;

slv_reg_write_select <= Bus2IP_WrCE(0 to 0);
slv_reg_read_select <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);

-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_select is
when "1" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0 ) is
begin

case slv_reg_read_select is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;


INTR_PROC : process( Bus2IP_Clk ) is
constant COUNT_SIZE : integer := 30;
constant ALL_ONES : std_logic_vector(0 to COUNT_SIZE-1) := (others => '1');
variable counter : std_logic_vector(0 to COUNT_SIZE-1);
begin

if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
counter := (others => '0');
interrupt <= (others => '0');
else
counter := counter + 1;
if ( counter = ALL_ONES ) then
interrupt <= (others => '1');
else
interrupt <= (others => '0');
end if;
end if;
end if;

end process INTR_PROC;

IP2Bus_IntrEvent <= interrupt;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;

IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';

end IMP;
--------------------------------------------------------------------

[heritage]

I think push buttons are active low  ie saves power

You still have more work

[dongtrungthao]

Thank your reply