The design I am creating consists of a microblaze, a clocking wizard, a processor system reset, an AXI interconnect, an uartlite and some local memory. The microblaze is configured to provide AXI stream interfaces.
When right click on these interfaces and chose "make external" and verify the design afterwards, I receive a message because no clock port is associated to the external AXI stream ports.
Therefore, I created an external clock port by right clicking and choosing "Create Port..." with type clock and direction output.
When I try assign a clock port to the AXI stream port via the "External Interface Properties", I receive the following error message:
Vivado v2014.4 (64-bit)
ERROR: [Common 17-70]: HTCProjectCommands::setCurrentProject
- null run pointer.
I get this message only after the first attempt, but my selection is never remembered. (These steps are discribed here: http://www.xilinx.com/support/answers/56609.html ) To create an input clock port is not working, too.
Is the design migrated? Null pointer exceptions ocurs when the tool is trying to access something which is not present.
Can you run the same commands in tcl console and see if the same issue persists?
the design is not migrated. It is created in Vivado 2014.4.
I am not sure which command I should try to run in the TCL console. The command setCurrentProject seems to be invalid.
I tried to make an AXI4 master port external as described in http://www.xilinx.com/support/answers/56609.html, but with the same result. It is also the same when I use a Zynq Processing System instead of a MicroBlaze and when I try it on a different system but with the same setup (Win7x64, Vivado 2014.4), too.
I tried it with an Ubuntu installation and there is no error when I asign the clock port, thus it seems to work. But, since I work on a Windows machine it would be nice to have a solution or at least some kind of workaround.
I have to correct myself. The version which works under Ubuntu is 2014.2. I installed 2014.4 under Ubuntu too, but when I create the project I receive the same error. Vivado 2014.4 is working under Windows, too.
Therefore, I think it is a bug in Vivado 2014.4.
For those who cares you can fix this with followed method:
Every block design which are generated with the IP integrator has in the sources/bd directory a corresponding *.bd file.
In that file you must search about your clock name and manually edit/extend under the ASSOCIATED_BUSIF parameter your busname to which the clock belongs.
The clock port "GP0_TX_AXI_clk" belongs to the AXI buses TXRAM_MAC_AXI:TX_S0_AXI:MIG_TXRAM_AXI:Zynq_TX_AXI_out
After you edit this you will see in the IP integrator when you click on the AXI bus port under clock-port the associated clock.
Or in the IPI gui, select the clock port, select properties and expand CONFIG. Manually type in the name of the axi port beside ASSOCIATED_BUSIF
I have tested this with v2015.1 of the tools which is due for early April release and I can confirm that this is not seen in the newer tools.
For now you may use one of the above workarounds for this issue.