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Observer karvi_in
Observer
11,023 Views
Registered: ‎11-14-2009

Instantiating VHDL module written in a seperate .vhd file

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Hi,

 

      I have two files in the pcores>hdl>vhdl folder

 

1) "vga_controller_vhdl.vhd"  the main file(created through EDK) which communicates with Microblaze through FSL and

 

2) "vga_controller_640_60.vhd" file that contains the timing generator module "vga_controller_640_60" .

 

Can someone point how I could link these two?

 

      I have instantiated the vga_controller_640_60 module in the 1st file as follows

 

 

 

library vga_controller_vhdl_v1_00_a;
use vga_controller_vhdl_v1_00_a.ALL;

 

 

architecture EXAMPLE of vga_controller_vhdl is

---
---

---

---

 
    component vga_controller_640_60
      port ( rst       : in    std_logic;
             pixel_clk : in    std_logic;
             hs        : out   std_logic;
             vs        : out   std_logic;
             blank     : out   std_logic;
             hcount    : out   std_logic_vector (0 to 10);
             vcount    : out   std_logic_vector (0 to 10));
   end component;
    
 
    

begin


   VgaCtrl640_60 : vga_controller_640_60
      port map (pixel_clk=>CLK_25MHz,
                       rst=>FSL_Rst,
                       blank=>bitBlank640_60,
                       hcount(0 to 10)=>vecHcount_640_60(0 to 10),
                       hs=>HS,
                       vcount(0 to 10)=>vecVcount_640_60(0 to 10),
                       vs=>VS);

 

---

---

--- other code

--- 

 

end architecture EXAMPLE;

 

 

 

 

----Contents of vga_controller_vhdl_v2_1_0.pao

 

##############################################################################
## Filename:          G:\Electronics\FPGA\EDK_Projects\Test1\pcores/vga_controller_vhdl_v1_00_a/data/vga_controller_vhdl_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Sat Dec 12 15:17:00 2009 (by Create and Import Peripheral Wizard)
##############################################################################

lib vga_controller_vhdl_v1_00_a vga_controller_640_60 vhdl          ## I added this line here
lib vga_controller_vhdl_v1_00_a vga_controller_vhdl vhdl

 

 

 

 

 

 When I compile I get this error:

 

   'vga_controller_vhdl_0/vga_controller_vhdl_0/VgaCtrl640_60' with type
   'vga_controller_640_60' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, or the misspelling of a type name.
   Symbol 'vga_controller_640_60' is not supported in target 'spartan3e'.
make: *** [__xps/system_routed] Error 1

 

 

 

 

Regards,

 

 Karthik

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1 Solution

Accepted Solutions
Observer karvi_in
Observer
12,299 Views
Registered: ‎11-14-2009

Re: Instantiating VHDL module written in a seperate .vhd file

Jump to solution

 

I had initially added the  "lib vga_controller_vhdl_v1_00_a vga_controller_640_60 vhdl", at the end of the file and saw the error message. I corrected this by putting it before the main module's lib line. But the error persisted. Today morning, I used the "clean hardware" command and "rescanned the user peripheral" and it worked. It seems that  "clean hardware" is required whenever changing anything in the pcore other that the hdl code. EDK apparently scans only the hdl files for changes during compile.

 

 

##############################################################################
## Filename:          G:\Electronics\FPGA\EDK_Projects\Test1\pcores/vga_controller_vhdl_v1_00_a/data/vga_controller_vhdl_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Sat Dec 12 15:17:00 2009 (by Create and Import Peripheral Wizard)
##############################################################################

lib vga_controller_vhdl_v1_00_a vga_controller_640_60 vhdl          ## I added this line here
lib vga_controller_vhdl_v1_00_a vga_controller_vhdl vhdl

 

 

Thanks guys.

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4 Replies
Scholar drjohnsmith
Scholar
11,009 Views
Registered: ‎07-09-2009

Re: Instantiating VHDL module written in a seperate .vhd file

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Hi

 

I think you might need toi take a step back,

 

You don't need this level of  explicitly.

 

Have you looked at the demo files ?

 

try a simple new project, create say an and gate, and call that up from a second file.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
11,003 Views
Registered: ‎07-15-2008

Re: Instantiating VHDL module written in a seperate .vhd file

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This may be of some use.

 

http://www.xilinx.com/support/answers/18385.htm

 

Kind Regards Bobster

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Observer karvi_in
Observer
12,300 Views
Registered: ‎11-14-2009

Re: Instantiating VHDL module written in a seperate .vhd file

Jump to solution

 

I had initially added the  "lib vga_controller_vhdl_v1_00_a vga_controller_640_60 vhdl", at the end of the file and saw the error message. I corrected this by putting it before the main module's lib line. But the error persisted. Today morning, I used the "clean hardware" command and "rescanned the user peripheral" and it worked. It seems that  "clean hardware" is required whenever changing anything in the pcore other that the hdl code. EDK apparently scans only the hdl files for changes during compile.

 

 

##############################################################################
## Filename:          G:\Electronics\FPGA\EDK_Projects\Test1\pcores/vga_controller_vhdl_v1_00_a/data/vga_controller_vhdl_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Sat Dec 12 15:17:00 2009 (by Create and Import Peripheral Wizard)
##############################################################################

lib vga_controller_vhdl_v1_00_a vga_controller_640_60 vhdl          ## I added this line here
lib vga_controller_vhdl_v1_00_a vga_controller_vhdl vhdl

 

 

Thanks guys.

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Visitor embesys
Visitor
1,998 Views
Registered: ‎07-24-2015

Re: Instantiating VHDL module written in a seperate .vhd file

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Here  

 

I am new to vhdl and xilinx to ...Here I want to combine two.vhd file in my xilinx project ... I have attached both the files..Can you please give me any hint???

 

Thanks in advance...

 

Have a nice a day..

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