Issues with multiple custom cores sharing same IIC bus (wrt VGA input and TFT core output)
I have some issues with AD9980 VGA input chip on ML505 using EDK 12.2. The reference design is pretty easy for DVI out using built in TFT controller. I adapted this for my own design and could use it in my application. I am using TFT IP core in my controller to display 640x480 images from DDR2 (although I would like to use it to display images supported for max resolution of the Chrontel CH7301C). I would like to use an instance of IIC core for communicating with the VGA input chip while retaining TFT IP core. Now the issue is the SDA and SCL (video IIC pins - specified by external port in XPS) are already utilized by TFT core and instance of IIC core need pins to be specified in "mhs" file. I cannot share those same signals (SDA and SCL) on two cores (TFT and IIC) else I receive fatal error of "multi-source" driving two cores (I believe underneath XPS GUI, each IP core is treated as a separate process like in ISE VHDL code. Hence it becomes illegal alloting same signal to two processing which may result in contention). Is there a way I can use current SDA and SCL pins specified in mhs and ucf file for TFT core in IIC core? What is the best way to assign multiple custom cores to same IIC bus core (since this is memory mapped IO)? I want to store VGA input image in DDR RAM (frame buffer) and display that using TFT core.