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Visitor zhbeagle
Visitor
2,770 Views
Registered: ‎04-12-2012

ML505 V5LX110T

Hello,

 

I have a  ML505 V5LX110T board ,but I have encountered problems when using the reference designs here

http://www.xilinx.com/products/boards/ml505/ml505_92i/reference_designs.htm,I know it's because the diferent pin of V5LX110Tand V5LX50T.

Could somebody give me a solution?

 

best regards

 

 

 

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2 Replies
Xilinx Employee
Xilinx Employee
2,752 Views
Registered: ‎08-13-2007

Re: ML505 V5LX110T

You don't detail what specific issues you are having, but if the design uses transceivers (GTP) - they will need to be adjusted:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/How-to-assign-the-bankless-pins/m-p/227013

 

If the design uses other die-based coordinates (e.g. IDELAYCTRL) - I could imagine similar issues.

 

The regular SelectIO should be fine, which is why I assume it is the transceivers since you reference the pin-out.

 

bt

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Scholar austin
Scholar
2,746 Views
Registered: ‎02-27-2008

Re: ML505 V5LX110T

z,

 

You have a XUPV5 pcb, NOT! a ML505.  They are similar, but they have different schematics, and different design libraries.

 

Go find the XUPV5 documentation, and use that, NOT the ML505.

 

http://www.xilinx.com/univ/xupv5-lx110t-refdes.htm

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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