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Explorer
Explorer
2,111 Views
Registered: ‎03-25-2010

MPMC: SRL or BRAM Fifo

Hello,

 

In the documentation of the MPMC you said: "However, in some cases, an SRL FIFO can improve system
timing versus a block RAM FIFO when the MPMC has a LARGE NUMBER of ports and routing to the block
RAMs results in excessive net delays".

 

Above how many ports can we consider a large number?

 

Thanks.

 

Regards,

 

DABG.

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1 Reply
Xilinx Employee
Xilinx Employee
2,099 Views
Registered: ‎07-30-2007

Re: MPMC: SRL or BRAM Fifo

Only worry about this if you are failing timing,(or are nearly failing timing) which is what this is referring to.  Throughput is generally better with BRAM FIFOs.  The large number of ports depends on the architecture, memory device type and phy considerations, see the BRAM utilization table in the datasheet.

 

Just realize it is a another knob you can turn to help timing closure or save BRAM utilization. Otherwise, just stick with the default BRAMs.

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