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Adventurer
Adventurer
4,536 Views
Registered: ‎11-07-2007

MPMC

Hi, I'm using ISE 10.1 SP3, EDK, SDK.  all of my tools are up to date.  I'm using a V4FX100 fpga. I have an ISE design that instantiates XPS project.  I'm using a uBlaze processor and external DDR2 SDRAM. 

 

what works:  I added a MPMC to my XPS project.  The first port is for the plb,  the 2nd and 3rd are for the uBlaze XCL ports.  I made a simple program in SDK.  the program was executed from external memory successfully.

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I added a 4th port to the MPMC; it's a NPI interface.  I want to access the DDR2 memory from logic located in my ISE project (outside of XPS).  I followed the directions and timing diagrams from the MPMC datasheet.  I made all of the PIM3## ports external so that they can be accessed by ISE.  I wrote some simple logic to write and read the memory through the NPI interface.  I chipscoped my design: I saw the init_done go high, I saw the addr_ack go high.  

 

what doesn't work:  I can't seem to verify that anything was written to memory.  the RdFIFO_empty signal is always high and my RdData signal is always zero.   Also, I tried to make the WrFIFO_almost_full signal go high, but i cannot. 

 

what am I doing wrong??  I tried to do single 32-bit writes and reads, and 8 32-bit writes and reads; neither of them work

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Visitor
Visitor
4,200 Views
Registered: ‎01-14-2009

I'm using the NPI bus for my custom module in my EDK project and I'm experiencing the same problem. RdFIFO_Empty signal never goes low even after I request to read. I do however get the AddrAck signal after sending proper signals. I followed the timing diagrams from the MPMC data sheet exactly the way they were shown. Can someone please explain why RdFIFO_Empty signal stays high?
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Anonymous
Not applicable
3,144 Views

I've had the same problem finally I've managed to solve it. The problem was:  in my first design AddrReq signal was high for one cycle but in fact it must be high until AddrAck received when I've changed the state machine and it began working.. 

 

here there is some  possible faults that I've encountered and the solutions for them..

 

check the clock sources: npi clk must be same with MPMC_CLK0 otherwise it won't work even if you get InitDone signal...

check connections: in RTL schematic and don't left any pins of NPI unconnected. if you see any unconnected pins check mpd file and correct it.. in my design I've realised that in .mpd file I wrote Addr_Req instead of AddrReq so the AddrReq signal was unconnected.

and check the adress values for example if you use 64bit burst mode address values must be integer  mutiples of 80h otherwise it won't work..

 

thats all I can say for now.. 

 

good luck... 

 

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