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Contributor
Contributor
1,545 Views
Registered: ‎03-20-2018

MPSoC Bare Metal applications on 2 APUs

I'm migrating an Zynq 7000 based design to a Zynq Ultrascale+ MPSoC platform. The Zynq design used both of the A9 processors running bare metal and was based on some code provided with XAPP1079 to permit CPU0 to bring up and start CPU1. There's also some mention that the FSBL had to be edited to allow for two processors running bare metal code. I've tried following the example but it seems like the SLCR structures seem to be rather different between the 7000 and the MPSoC. 
 
Are there any resources for describing how to bring up two or more CPUs running bare metal code on the MPSoC? Perhaps something equivalent to XAPP1079 for the MPSoC? The SLCR registers for the MPSoC seem to be very different from the Zynq 7000 versions, so it isn't obvious how to change the XAPP1079 to work for the MPSoC even though it's only a very instructions required. Also, XAPP1079 says to select Zynq FSBL for AMP, but there doesn't seem to be any equivalent to this in my Zynq MPSoC SDK project. I don't need a whole XAPP, which I suspect is not available, but some pointers regarding the FSBL and which SCLR registers/bits are needed to start up CPU1 would be very helpful.
 
 
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Scholar
Scholar
1,517 Views
Registered: ‎04-13-2015

@barrygmoss

I think this piece of code is what your are looking for.  It is what we use in our RTOS to get the 3 other cores up and running.  As for BSP set-up (I am aware changes must be done for the 70XX), I can't be of any help as the RTOS does not use it.

    MOV64    x1, _vector_table
    MOV64    x2, 0xFD5C0040                    // Base address of the RVBAR registers
    str      x1, [x2]                          // Put _vector_table in my RVBAR

    MOV64    x3, 0xFD1A0104                    // RST_FPD_APU register base address
    ldr      w4, [x3]
    orr      w4, w4, #(7 << 1)                 // Hold cores #1, #2 & #3 in reset
    str      w4, [x3]
    bic      w4, w4, #(7 << 11)                // Remove the power-on reset on cores #1 #2 & #3
    str      w4, [x3]

    str      x1, [x2, #8]                      // Set-up RVBAR for core #1
    str      x1, [x2, #16]                     // Set-up RVBAR for core #2
    str      x1, [x2, #24]                     // Set-up RVBAR for core #3

     bic      w4, w4, #((1 << (OS_N_CORE))-2)  // -2 instead of -1 to not reset core #0
    str      w4, [x3]                         // Only OS_N_CORE are left running

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Contributor
Contributor
1,476 Views
Registered: ‎03-20-2018

Thanks for your suggestion, but how would I add assembler code to a C project in SDK?

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Scholar
Scholar
1,440 Views
Registered: ‎04-13-2015

@barrygmoss

Nothing really fancy is done in that code, it's mostly reading and writing 32 bit registers. Read with

Value = *((volatile int32_t *)0x12345678LL);

and write with

*((volatile int32_t *)0x12345678LL) = Value;

 

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Xilinx Employee
Xilinx Employee
1,368 Views
Registered: ‎10-06-2016

Hi @barrygmoss

Did you take a look to the UG1186 where openAMP is described? Xilinx does provide support for the OpenAMP framework and SDK and Petalinux integrates some example on how it can be used.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Contributor
Contributor
1,345 Views
Registered: ‎03-20-2018

I did indeed look at openAMP as a solution, but switching this project over to Petalinux would be a significant challenge. Having looked over the options, I think that the best course would be to take the code that was running on the second CPU and turn it into an ISR. We made the switch from the Zynq to the Zynq Ultrascale+ not because of a requirement for more processing power but rather because we needed a larger DDR memory space. I think the single A53 will be able to handle everything.

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Participant
Participant
1,147 Views
Registered: ‎10-12-2009

Hello,

some basic demo you can find at https://github.com/topalovicdraganl/nativeAMP

BR

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