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Registered: ‎11-04-2009

Maybe an easier way to integrate hardware register map based IP into PPC or uBlaze platform?

Hi all,


For my entire time working on systems with Microblaze or PowerPC on Xilinx chips, I've been thinking that it's quite a hassle to make custom IP cores using the user IP core generator.


My reason, of course, is that any time you make a change to the IP, there are several places that might need to be edited. Suppose you want to add one port that goes out to your FPGA fabric. You have to edit the two source files buried deep inside the pcores folder of your EDK directory. Then, if I remember right to edit the MPD for your core, and you have to edit your system's MHS file, as well as the component decaration and instantiation of your processor system in your top level VHDL or Verilog module.

I think the core of this issue is that the current scheme is an attempt to abstract the PLB bus, which resulted in something more complicated and less flexible (in my opinion).

I have for now alleviated this by figuring out how many registers I thought I would need, and adding a good margin on top of that, and bringing them out to the top level in the beginning, so I could use the extra registers whenever I needed to add something.


Depending on how it's done, perhaps you could lose a little bit of performance or area, but why not just use the Extermal Memory Controller, which gives you address, data, read/write, and chip select, then do the address decoding in your own code? Then if you want to add something to the memory map, you add it in one place and it's done. The process can and should be synchronous to your main system clock, and based on the timing waveform of the EMC IP.


The other solution, of course, would be to bring out the PLB signals and write your IP to be PLB compliant, but using the EMC seems simpler to put together from scratch if you don't already have a PLB wrapper ready to drop your registers into. And I kind of doubt that the EMC would use that much fabric. I already have one in the system I've been working on, with a couple of unused channels, so I would think about switching to this scheme if I didn't already have the "custom IP" with more registers than I needed.


This is just an idea I thought I'd throw out there, anybody have any thoughts on this?



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Xilinx Employee
Xilinx Employee
Registered: ‎08-06-2007



Personally when I need an IP which only is accessed with simple read and write, I code everything from scratch.

When I have done one module for a specific bus, I can use that and change it for other IP on the same bus.

I have found that this is easier than trying to understand a other IP interface layer.

With AXI4-Lite, it's very few signals that is used and not much code is needed.


However if I was to create something that used the bus with all it's features I would most likely use the IPIF since then it's not just simple reads and writes.



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