UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
10,848 Views
Registered: ‎03-16-2009

MicroBlaze Max Frequency?

my referene clk is 50MHz. how much frequency can i set for MB?

the MB's version is 7.00.a and i am in EDK9.2.

0 Kudos
16 Replies
Xilinx Employee
Xilinx Employee
10,829 Views
Registered: ‎08-13-2007

Re: MicroBlaze Max Frequency?

There is no simple answer here. It depends on a number of variables:

-family (Virtex-5 is very different than Spartan-3E)

-device and speed grade

-processor configuration (3 vs 5 stage pipeline, floating point, etc.)

-number and type of bus peripherals

-synthesis and implentation options, including tool setttings, any florplanning, etc.

-how much effort you are wiling to spend reaching timing closure.

 

100MHz is possible on Spartan-3E but is likely not easy or push button. 50 or 66MHz seems to be much more common in my experience.

 

bt

0 Kudos
10,491 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

My question is kind of related (in my opinion)...

I have created a custom peripheral in EDK which uses the PLB 4.6 Bus...using Spartan 3 starter board with xc3s200 device in ft256 package, speed grade -4. Now I have tested my peripheral in ISE and it takes 5 cycles of my reference 50MHz clock to write to my peripheral for example:

 

if I use

 

XGpio_mSetDataReg(LCD_BASEADDR, 1, 0x00000002);

XGpio_mSetDataReg(LCD_BASEADDR, 1, 0x0000000f); 

 

In my software application code...the 0x00000002 value changes to 0000000f after 5 clock cyles have elapsed (100ns)...If I want to reduce the time...what should I do? Should I go for increasing the clock frequency? Or should I use some other faster C function or bus standard or other approach? All I want to do is have microblaze write some data to a top level ISE module (a memory controller in my case)...the guys at the forums told me my best bet was to use a PLB based custom peripheral...So please shed some light...my goal is to minimize the time taken between two successive write commands...I am using a 5 stage pipeline (Area optimization disabled)...any other microblaze parameters that I need to change?

0 Kudos
Xilinx Employee
Xilinx Employee
10,476 Views
Registered: ‎08-06-2007

Re: MicroBlaze Max Frequency?

Hi,

 

 

The PLB bus itself have a latency of at least 5 clock cycles.

You can't get lower than that.

 

If I was you, I would have used the FSL bus since it takes two clock cycles for each put instruction.

I would have connected fsl0_m_data and fsl0_m_write to your ISE design.

The input signal fsl0_m_full could be connected to '0' if your ISE design always can accept new data.

In MicroBlaze I would execute two PUT instructions after each other. You would see two clock cycles between each write on the FSL bus.

 

Göran

10,466 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

For the PLB peripheral...I was following a tutorial which showed how to make the custom ip's port external and how to modify its data width and how to modify the ip.vhd and user_logic.vhd files etc...I am a Verilog person and don't know VHDL...Is there a similar tutorial for creating a FSL based peripheral? My requirement is 32 bits for data...18 pins for address and not more than 2 control signals(most likely 1)...all will be external from the peripheral...my focus is on only writing to the peripheral not reading from it...so please guide me to some documents...I have created an FSL based peripheral using Create and Import Peripheral Wizard with 2 32 bit input registers...but I don't know how to proceed...

 

Also you mentioned the PUT instruction...sounds like Assembly Language to me...uptill now I have only worked with MicroBlaze in C...Do I just replace the.c file in my Software Application Project with an assembly file and rebuild it? Also please provide me with some links to a sample MicroBlaze Assembly language code...

0 Kudos
Xilinx Employee
Xilinx Employee
10,446 Views
Registered: ‎08-13-2007

Re: MicroBlaze Max Frequency?

You may find these useful:

http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf (Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link (FSL) Channel)
http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=7822 (how to read/write data from FSL?)

Cheers,

bt

10,431 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

Thank you timpe...But I still need to know how to make the ports external...like I said...I dont know VHDL...so how can I modify my FSL based custom IP's ports external and assign them to the incoming data from the processor? I tried editing the MPD file...but the port I declared in the MPD did not appear in the ports view in XPS after I rescanned the user repositories and added the IP to my design... 
0 Kudos
10,382 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

There is an option of generating the wrapper file in Verilog...I ticked it...lets see what happens...
0 Kudos
Xilinx Employee
Xilinx Employee
10,355 Views
Registered: ‎08-06-2007

Re: MicroBlaze Max Frequency?

Hi,

 

No need to make a FSL peripheral if you only going to use it as a GPIO.

 

Just make these MicroBlaze signals external in XPS

FSL0_M_Clk

FSL0_M_Write

FSL0_M_Data

FSL0_M_Full

 

If your ISE design is using the same clock as MicroBlaze, you dont need to make the FSL0_M_Clk external.

If you don't need to throttle MicroBlaze writes on this port, just connect FSL0_M_Full to ground, otherwise this signal is the throttle signal.

When MicroBlaze executes a PUT instruction it will assert FSL0_M_Write one clock cycle and the 32-bit data will be on the FSL0_M_Data signal.

 

 

Göran

0 Kudos
10,344 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

Uh huh...just one more thing...is the putfsl(val,id) function in C the same as the PUT instruction in assembly? Or does it take more clock cycles to execute?
0 Kudos
6,267 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

I tried doing what you suggested (trying to make the microblaze master signals themselves external)...how do I do this? I know it must be simple but I just can't figure it out!!! If I click on MFSL0 in the Bus Interfaces tab I get the Make New Connection Option which I don't want cause it will insert an FSL IP core in the project...which is what I was doing earlier...
0 Kudos
Xilinx Employee
Xilinx Employee
6,249 Views
Registered: ‎08-06-2007

Re: MicroBlaze Max Frequency?

Hi,

 

Don't connect them as a bus. Connect them as individual signals.

Like this: 

 

PARAMETER VERSION = 2.1.0

 

 

 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000

 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1

 PORT Data = FSL0_M_Data, DIR = O, VEC = [0:31]

 PORT Write = FSL0_M_Write, DIR = O

 PORT Full = FSL0_M_Full, DIR = I

 

BEGIN microblaze

 PARAMETER INSTANCE = microblaze_0

 PARAMETER C_FAMILY = spartan3

 PARAMETER C_AREA_OPTIMIZED = 0

 PARAMETER C_INTERCONNECT = 1

 PARAMETER C_DEBUG_ENABLED = 0

 PARAMETER HW_VER = 7.20.b

 PARAMETER C_FSL_LINKS = 1

 BUS_INTERFACE DLMB = dlmb

 BUS_INTERFACE ILMB = ilmb

 PORT MB_RESET = mb_reset

 PORT FSL0_M_Data = FSL0_M_Data

 PORT FSL0_M_Write = FSL0_M_Write

 PORT FSL0_M_Full = FSL0_M_Full 

END

Explorer
Explorer
6,245 Views
Registered: ‎10-01-2007

Re: MicroBlaze Max Frequency?

Hello.

I would like to ask by the same theme - putfslx function about. I cannot find detailed information about these functions.

It was mentioned here that putfsl function takes 2 clocks.  So, if I want to send for example data - 32 words (float data[32]={0,1,2,3...31}) to pcore (from microblaze per FSL) with NONBLOCKING option, I use for loop for it:

 

for(i=0;i<32;i++){ putfslx(data(i),0,FSL_NONBLOCKING);

}

 Do i need worry FIFO buffer, how to know when it's possible to put second word of data? Does such loop is right solution? If full piece of data was send to FSL and pcore takes it how to know time when microblaze can use getfslx? For example CORDIC sqroot, FFT has outputs like rdy. Does I need to read it?

It's right when sharpish after putfslx loop i use getfslx loop?

 Thanks

 

Best Regards,
Vytautas
0 Kudos
Xilinx Employee
Xilinx Employee
6,235 Views
Registered: ‎08-06-2007

Re: MicroBlaze Max Frequency?

Hi,

 

MicroBlaze FSL is a interface with FIFO-like handshake signalling.

MicroBlaze will not write to FSL (put) if the FULL flag is high and MicroBlaze will not read from FSL (get) when EXISTS flag is low.

You can make MicroBlaze to freeze on these stall conditions (blocking) or setting a flag in MSR (non-blocking).

 

Xilinx provides a fsl_v20 bus which is essential a FIFO to make it easier to connect a FSL master to a FSL slave.

A FIFO provides a buffer between the two interfaces so they don't have to be ready to transmit and receive at the same clock cycle.

 

If your slave is a GPO which always will accept new data, there is no need for the FULL flag and thus also no need for a FIFO (fsl_v20 bus).

If your master is a GPI which always have new data, there is corresponding no need for a EXISTS flag.

This was the case for the system for this thread.

 

If your slave or master do have a handshake signalling, it must match with the FSL signalling or you have to create glue-logic.

 

I don't know about your cordix core but if it has signals for trottling data, you must either be sure that the whole data fits in the FIFO inside fsl_v20 or you have to throttle your cordix with the fsl handshake signal.

 

There is not one solution to glue together interface, most core have a slightly different handshake signalling and for most cases some simple glue logic is needed.

You have to look at the waveform or reading data sheet to understand the signalling for each core and see how they map to FSL.

 

Göran

Message Edited by goran_bilski on 09-01-2009 01:41 PM
Message Edited by goran_bilski on 09-01-2009 01:43 PM
6,221 Views
Registered: ‎07-06-2008

Re: MicroBlaze Max Frequency?

It works...the MHS contents you proposed did the trick...but for some reason it take 3 clock cycles between each putfsl execution...wonder why that is?
0 Kudos
Xilinx Employee
Xilinx Employee
6,202 Views
Registered: ‎08-06-2007

Re: MicroBlaze Max Frequency?

Hi,

 

Look at the machine code by disassembling your .elf file.

It will tell you why. 

 

Göran

0 Kudos
Newbie andrewd220
Newbie
215 Views
Registered: ‎07-03-2018

Re: MicroBlaze Max Frequency?

Hi Barrie!

0 Kudos