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Anonymous
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Microblaze leve versus Edge Interrupt

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Hi,

 

I have a source code which simulates interrupt controller to generate interrupt by writing interrupt status (ISR) register of GPIO. This code works perfectly fine when I use "LEVEL" interrupt on microblaze. 

 

However, this code stops working as soon as I change the interrupt controller from "LEVEL" to "EDGE". When I use edge someteimes, it catches and handles interrupts, sometimes it never catches interrupts, and sometimes it catches several interrupts (more than what I am generating). 

 

Does anyone have any ideas ? 


- Is there a simple example to simulate EDGE based interrupt controller ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-08-2010

Thanks for providing the screenshot and the results of running the commands.

 

This confirms that the issue is what I suspected, and it also shows that you have inputs to the two AXI Intc that are not "proper" interrupts, i.e. do not have the SENSITIVITY property.

 

To correct this, you need to do two things:

 

1. Do not manually set "AckBeforeService" in your code. The documentation you quote refers to the AXI Intc interrupt inputs, not to the setting of the AXI Intc output connected to MicroBlaze (below "Processor Interrupt Type" in the dialog, corresponding to parameter CONFIG.C_IRQ_IS_LEVEL). The "AckBeforeService" value for each interrupt is determined from the type of the interrupt input (using parameter CONFIG.C_KIND_OF_INTR), and is generated automatically from the hardware description in SDK by the Intc driver. When you are connecting IP cores with SENSITIVITY parameters on their pins, the parameter CONFIG.C_KIND_OF_INTR is set according to the type of each interrupt when the Block Design is validated. In your case the value of this parameter can be seen in the GUI: "Interrupts type - edge or level 0xFFFFFF82. The SENSITIVITY of each interrupt source determines whether it should be handled as level or edge.

 

2. Check the interrupt inputs that lacks the SENSITIVITY property, and verify if the automatic assignment as Rising Edge is appropriate. The relevant warning messages from the two AXI Intc when validating the design are:

 

WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_mb_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interupt type Rising Edge. Please change this manually if necessary.

WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_PCIe_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interupt type Rising Edge. Please change this manually if necessary.

 

IF you need to change it manually, you have to click on the respective "Auto" buttons in the dialog to change it to "Manual". To use Level High change the value of "Interrupts type - edge or level" to 0xFFFFFF8A. If you want falling edge, you instead need to change "Edge Type - Rising or Falling" to 0xFFFFFFF7. If you want Level Low, change both "Interrupts type - edge or level" to 0xFFFFFF8A and "Level Type - High or Low" to 0xFFFFFFF7.

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Anonymous
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Hi All,

 

Regarding my question above, I want to post more details here. Basically, I have a code that works for the following setup.

 

Setup 1:

- GPIO writes to ISR with (Xil_Out32(0x00020120, 1);) to generate an level interrupt.

- Interrupt Controller which is setup to generate (output) LEVEL interrupt catches the interrupt and calls interrupt handler.

- Interrupt Handler clears/acknowledges the interupt controller inside the interrupt handler.

 

Setup 2:

- GPIO writes to ISR with (Xil_Out32(0x00020120, 1);) to generate an level interrupt.

- Interrupt Controller which is setup to generate (output) EDGE interrupt catches the interrupt and calls interrupt handler. 

- I manually set AckBeforeService  to acknowledge before service since this is an EDGE interrupt. 

 

 

Currently, Setup  2 does not work for some reason. I am wondering if there are any one who can comment on this ?Only difference between Setup 1 and Setup 2 is LEVEL/EDGE on interrupt controller.

 

Thanks,

Janarbek.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

What version of the tools and IP are you using?

 

Göran

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Anonymous
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I am using Vivado 2014.3.1 

 

AXI INTC 4.1 

AXI GPIO 2.0

Microblaze 9.4 

 

Again the code attached (works) when I use "LEVEL" on AXI INTC 4.1, but it stops working once I set "EDGE" on AXI INTC 4.1. I know I have to achnowledge before service when we use "EDGE" in order not to looseinterrupts. I already set it.  But it is not working for some reason. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

Could you provide your Vivado design?

 

Göran

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Anonymous
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Hi,

 

Unfortunetely, the design is big and I do not think I can share the design at this point. 

 

Baiscally, C code just works fine with "Level" interrupt, but stops working with "Edge" interrupt. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

What steps do you do when you change the interrupt from "Level" to "Edge"?

 

Göran

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Anonymous
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Hi Gohan,

 

From AXI INTC controlller, I changed interrupt type from "level" to "Edge", and re-compiled and generated bitstream.  That is all I did different than previous (working) design. Also I do not think changing to "edge" should cause a problem. I believe the problem is related to AXI INTC APIs in the SDK. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

After you did the HW change on the AXI_INTC, did you also generated a new hardware spec for the SDK and recompiled the code?

 

Göran

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-08-2010

Assuming that you are using Vivado IP Integrator and that I understood your description correctly, the issue might be that you are changing type under "Processor Interrupt Type" in the "Re-customize IP" dialog (parameter CONFIG.C_IRQ_IS_LEVEL), which defines the interrupt type between the AXI Intc and MicroBlaze.

 

If that is the case, you should not change the software to use "AckBeforeService". The "AckBeforeService" value is determined from the type of the interrupt inputs (parameter CONFIG.C_KIND_OF_INTR with one bit per interrupt), and should normally be generated automatically from the hardware description in SDK by the Intc driver. When you are connecting IP cores with SENSITIVITY parameters on their pins, such as a GPIO interrupt output pin, the parameter CONFIG.C_KIND_OF_INTR should be set according to the type of each interrupt when the Block Design is validated.

 

To check this, could you please post the results from the following Vivado Tcl commands with both the passing and failing configuration (change the name of the axi_intc instance from "microblaze_0_axi_intc" if necessary)?

 

validate_bd_design
get_property CONFIG.C_KIND_OF_INTR [get_bd_cells microblaze_0_axi_intc] get_property CONFIG.C_KIND_OF_INTR.VALUE_SRC [get_bd_cells microblaze_0_axi_intc]
get_property CONFIG.C_KIND_OF_EDGE [get_bd_cells microblaze_0_axi_intc] get_property CONFIG.C_KIND_OF_EDGE.VALUE_SRC [get_bd_cells microblaze_0_axi_intc]
get_property CONFIG.C_KIND_OF_LVL [get_bd_cells microblaze_0_axi_intc] get_property CONFIG.C_KIND_OF_LVL.VALUE_SRC [get_bd_cells microblaze_0_axi_intc]
get_property CONFIG.C_IRQ_IS_LEVEL [get_bd_cells microblaze_0_axi_intc] get_property CONFIG.SENSITIVITY [get_bd_pins microblaze_0_axi_intc/intr]

 

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Anonymous
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Hi Stefana,

 

1) Thanks for reply. Let me summarize my question agoin (althought it was posted above). We havea Vivado design that has microblaz, perhiperals (AXI GPIO), and interrupt controller. If I use "Edge" interrupt on INTC output, above attached C code does not work. However, If I use "level" interrupt on INTC output, the above code works fine (meaning that it catches interrupts generated by GPIO). 

 

Again the only difference is "edge" versus "level" between above two designs. Since I have used Vivado for a some time, I do not suspect some kind of errors such as not porting the design after synthesis.  

 

 

2) Anyway, I sent results for the commands you requested. Please see attached command_output.docx file. I also attached the screen shot of INTC IP core settings. 

 

 

3) Regardiing AckBeforeSerivice, I believe EDGE interrupts must be acknowledged before serivce. 

 

* The acknowledgement of the interrupt within the interrupt controller is
* selectable, either prior to the device's handler being called or after
* the handler is called. This is necessary to support interrupt signal inputs
* which are either edge or level signals. Edge driven interrupt signals
* require that the interrupt is acknowledged prior to the interrupt being
* serviced in order to prevent the loss of interrupts which are occurring
* extremely close together. A level driven interrupt input signal requires
* the interrupt to acknowledged after servicing the interrupt to ensure that
* the interrupt only generates a single interrupt condition.

 

InterrupSettings.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-08-2010

Thanks for providing the screenshot and the results of running the commands.

 

This confirms that the issue is what I suspected, and it also shows that you have inputs to the two AXI Intc that are not "proper" interrupts, i.e. do not have the SENSITIVITY property.

 

To correct this, you need to do two things:

 

1. Do not manually set "AckBeforeService" in your code. The documentation you quote refers to the AXI Intc interrupt inputs, not to the setting of the AXI Intc output connected to MicroBlaze (below "Processor Interrupt Type" in the dialog, corresponding to parameter CONFIG.C_IRQ_IS_LEVEL). The "AckBeforeService" value for each interrupt is determined from the type of the interrupt input (using parameter CONFIG.C_KIND_OF_INTR), and is generated automatically from the hardware description in SDK by the Intc driver. When you are connecting IP cores with SENSITIVITY parameters on their pins, the parameter CONFIG.C_KIND_OF_INTR is set according to the type of each interrupt when the Block Design is validated. In your case the value of this parameter can be seen in the GUI: "Interrupts type - edge or level 0xFFFFFF82. The SENSITIVITY of each interrupt source determines whether it should be handled as level or edge.

 

2. Check the interrupt inputs that lacks the SENSITIVITY property, and verify if the automatic assignment as Rising Edge is appropriate. The relevant warning messages from the two AXI Intc when validating the design are:

 

WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_mb_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interupt type Rising Edge. Please change this manually if necessary.

WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_PCIe_intc: Property SENSITIVITY = "NULL" for interrupt input 3 not recognized - using default interupt type Rising Edge. Please change this manually if necessary.

 

IF you need to change it manually, you have to click on the respective "Auto" buttons in the dialog to change it to "Manual". To use Level High change the value of "Interrupts type - edge or level" to 0xFFFFFF8A. If you want falling edge, you instead need to change "Edge Type - Rising or Falling" to 0xFFFFFFF7. If you want Level Low, change both "Interrupts type - edge or level" to 0xFFFFFF8A and "Level Type - High or Low" to 0xFFFFFFF7.

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Anonymous
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Hi Stefana,

 

Thanks for very helpful tips. 

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Visitor
Visitor
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Registered: ‎02-14-2019

Hi,

I have the same problem.

In the IP documentation, you have the following sentence:

Caution! Xilinx recommends that this settings is not changed from its value (0-level) when AXI INTC is connected to a Microblaze (AXI INTC v4.1 Product Guide p.38).

Did you find a solution for your issue?

Jérémy

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