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Registered: ‎09-02-2012

Microblaze on XUPV5-LX110T: Xflow error

Hi everyone,


I'm trying to do some research work involving embedded processor on FPGAs; however, I've been running into a ton of issues just with the initial stages of getting anything to work.


Board: XUPV5-LX110T

Software: ISE 12.2



Background: I was originally having issues with constraint errors because I was using the support files from this page, but it turns out that these don't seem to work because I got lots of constraint errors. Lurking around these forums, I found these support files, and these one's actually seem to work (or at least, I'm getting further along in the generate bitstream step from the tutorial above).


However, I'm still having issues. I attached the output from when I try to generate the bitstream to use with SDK. Basically, I get past the majority of placing and routing, and then, I seemingly randomly get the following error with little other information.


All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the   

constraint is not analyzed due to the following: No paths covered by this   

constraint; Other constraints intersect with this constraint; or This   

constraint was disabled by a Path Tracing Control. Please run the Timespec   

Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.


All signals are completely routed.


Total REAL time to PAR completion: 1 mins 55 secs

Total CPU time to PAR completion: 2 mins 1 secs


Peak Memory Usage:  983 MB

Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found.

Number of error messages: 0 Number of warning messages: 6 Number of info messages: 2


Writing design to file system.ncd




PAR done!

ERROR:Xflow - par: application received signal 11

ERROR:Xflow:42 - Aborting flow execution...

make: *** [__xps/system_routed] Error 1



I know that the board is a little old, but I'm determined to get this thing working, and your help would be greatly appreciated. If worst comes to worse, I could probably get a different (Virtex-6) board from my professor or change to a different SOC.

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Registered: ‎03-24-2008

I don't think this is a fix for the problem, but it's a workaround. I've seen the same error, but if you look closely at it, it says "PAR done." So, you can issue a command to continu the process, assuming PAR is done.


Looking at the system.make file, I did the following (from implementation directory):

$ bitgen -w -f ../bitgen.ut <name_of_project>


This should get you to the "Bitstream generation is complete." phase.

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