02-02-2017 02:22 AM
02-05-2017 07:04 AM
Could you please give more info on " below model (slightly complicated)"?
Are you following IP Packager flow for your IP?
02-05-2017 08:41 PM
HI Praveen, Thanks for the reply.
Sorry about the incomplete information.
I am using an example system generator design and exporting it as an IP core, specifying the AXI-Lite interface in Gateway In and Gateway Out ports.
Then I compile it as IP catalog and i integrate the thus generated IP core to zynq.
Later i send the image file through SDK to IP core. The program compiles. But when i print the values they are only zeros instead of integers.
I have attached the Matlab files and C (SDK) files. Please have a look at them.
Thanks a lot in advance..