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Explorer
Explorer
11,524 Views
Registered: ‎06-25-2008

PE Student Edition supports only a single HDL Error In Modelsim

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I finally got Modelsim to work with XPS and I can compile (c) in modelsim but when I type s in modelsim I get the following error "PE Student Edition supports only a single HDL".  Yes I am using the student addition but I believe everything was created in VHDL by XPS.  Can anyone give me any pointers?

Thanks,

DeWayne

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Xilinx Employee
Xilinx Employee
13,810 Views
Registered: ‎08-02-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hello,

 

That is the correct one.

 

If you look at the section  DDR_SDRAM of MHS, DDR is interfaced using MPMC. The HDL of this core is in Verilog.

 

You can check trying the simulation by commenting out the DDR SDRAM core.

 

HTH

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Xilinx Employee
Xilinx Employee
11,523 Views
Registered: ‎08-02-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hello,

 

Just wondering if you have any Custom Peripheral in Verilog or have MPMC in your design. Some of the hdl in MPMC core are in Verilog.

 

HTH,

Hem

 

 

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Explorer
Explorer
11,520 Views
Registered: ‎06-25-2008

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Nope, I haven't created any of my files just what is created by XPS.
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Xilinx Employee
Xilinx Employee
11,517 Views
Registered: ‎08-02-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hello,

 

Can you let us know how your MHS looks like ?

 

Regards.

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Explorer
Explorer
11,515 Views
Registered: ‎06-25-2008

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Is this the correct file?

 

# ##############################################################################

# Created by Base System Builder Wizard for Xilinx EDK 10.1.02 Build EDK_K_SP2.5

# Fri Aug 15 22:44:58 2008

# Target Board: Xilinx Spartan-3E Starter Board Rev C

# Family: spartan3e

# Device: XC3S500e

# Package: FG320

# Speed Grade: -4

# Processor: microblaze_0

# System clock frequency: 50.00 MHz

# On Chip Memory : 8 KB

# Total Off Chip Memory : 48 MB

# - FLASH = 16 MB

# - DDR_SDRAM = 32 MB

# ##############################################################################

PARAMETER VERSION = 2.1.0

 

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I

PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O

PORT fpga_0_RS232_DTE_RX_pin = fpga_0_RS232_DTE_RX, DIR = I

PORT fpga_0_RS232_DTE_TX_pin = fpga_0_RS232_DTE_TX, DIR = O

PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7]

PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3]

PORT fpga_0_Buttons_4Bit_GPIO_in_pin = fpga_0_Buttons_4Bit_GPIO_in, DIR = I, VEC = [0:3]

PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O

PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]

PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O

PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O

PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]

PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]

PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO

PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]

PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]

PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O

PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]

PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]

PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]

PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]

PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I

PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O

PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]

PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000

PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST

 

BEGIN microblaze

PARAMETER INSTANCE = microblaze_0

PARAMETER C_INTERCONNECT = 1

PARAMETER HW_VER = 7.10.c

PARAMETER C_DEBUG_ENABLED = 1

PARAMETER C_AREA_OPTIMIZED = 1

BUS_INTERFACE DLMB = dlmb

BUS_INTERFACE ILMB = ilmb

BUS_INTERFACE DPLB = mb_plb

BUS_INTERFACE IPLB = mb_plb

BUS_INTERFACE DEBUG = microblaze_0_dbg

PORT MB_RESET = mb_reset

END

BEGIN plb_v46

PARAMETER INSTANCE = mb_plb

PARAMETER HW_VER = 1.03.a

PORT PLB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_v10

PARAMETER INSTANCE = ilmb

PARAMETER HW_VER = 1.00.a

PORT LMB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_v10

PARAMETER INSTANCE = dlmb

PARAMETER HW_VER = 1.00.a

PORT LMB_Clk = sys_clk_s

PORT SYS_Rst = sys_bus_reset

END

BEGIN lmb_bram_if_cntlr

PARAMETER INSTANCE = dlmb_cntlr

PARAMETER HW_VER = 2.10.a

PARAMETER C_BASEADDR = 0x00000000

PARAMETER C_HIGHADDR = 0x00001fff

BUS_INTERFACE SLMB = dlmb

BUS_INTERFACE BRAM_PORT = dlmb_port

END

BEGIN lmb_bram_if_cntlr

PARAMETER INSTANCE = ilmb_cntlr

PARAMETER HW_VER = 2.10.a

PARAMETER C_BASEADDR = 0x00000000

PARAMETER C_HIGHADDR = 0x00001fff

BUS_INTERFACE SLMB = ilmb

BUS_INTERFACE BRAM_PORT = ilmb_port

END

BEGIN bram_block

PARAMETER INSTANCE = lmb_bram

PARAMETER HW_VER = 1.00.a

BUS_INTERFACE PORTA = ilmb_port

BUS_INTERFACE PORTB = dlmb_port

END

BEGIN xps_uartlite

PARAMETER INSTANCE = RS232_DTE

PARAMETER HW_VER = 1.00.a

PARAMETER C_BAUDRATE = 9600

PARAMETER C_DATA_BITS = 8

PARAMETER C_ODD_PARITY = 0

PARAMETER C_USE_PARITY = 0

PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000

PARAMETER C_BASEADDR = 0x84000000

PARAMETER C_HIGHADDR = 0x8400ffff

BUS_INTERFACE SPLB = mb_plb

PORT RX = fpga_0_RS232_DTE_RX

PORT TX = fpga_0_RS232_DTE_TX

END

BEGIN xps_uartlite

PARAMETER INSTANCE = RS232_DCE

PARAMETER HW_VER = 1.00.a

PARAMETER C_BAUDRATE = 9600

PARAMETER C_DATA_BITS = 8

PARAMETER C_ODD_PARITY = 0

PARAMETER C_USE_PARITY = 0

PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000

PARAMETER C_BASEADDR = 0x84020000

PARAMETER C_HIGHADDR = 0x8402ffff

BUS_INTERFACE SPLB = mb_plb

PORT RX = fpga_0_RS232_DCE_RX

PORT TX = fpga_0_RS232_DCE_TX

END

BEGIN xps_gpio

PARAMETER INSTANCE = LEDs_8Bit

PARAMETER HW_VER = 1.00.a

PARAMETER C_GPIO_WIDTH = 8

PARAMETER C_IS_DUAL = 0

PARAMETER C_IS_BIDIR = 0

PARAMETER C_ALL_INPUTS = 0

PARAMETER C_BASEADDR = 0x81400000

PARAMETER C_HIGHADDR = 0x8140ffff

BUS_INTERFACE SPLB = mb_plb

PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out

END

BEGIN xps_gpio

PARAMETER INSTANCE = DIP_Switches_4Bit

PARAMETER HW_VER = 1.00.a

PARAMETER C_GPIO_WIDTH = 4

PARAMETER C_IS_DUAL = 0

PARAMETER C_IS_BIDIR = 0

PARAMETER C_ALL_INPUTS = 1

PARAMETER C_BASEADDR = 0x81420000

PARAMETER C_HIGHADDR = 0x8142ffff

BUS_INTERFACE SPLB = mb_plb

PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in

END

BEGIN xps_gpio

PARAMETER INSTANCE = Buttons_4Bit

PARAMETER HW_VER = 1.00.a

PARAMETER C_GPIO_WIDTH = 4

PARAMETER C_IS_DUAL = 0

PARAMETER C_IS_BIDIR = 0

PARAMETER C_ALL_INPUTS = 1

PARAMETER C_BASEADDR = 0x81440000

PARAMETER C_HIGHADDR = 0x8144ffff

BUS_INTERFACE SPLB = mb_plb

PORT GPIO_in = fpga_0_Buttons_4Bit_GPIO_in

END

BEGIN xps_mch_emc

PARAMETER INSTANCE = FLASH

PARAMETER HW_VER = 2.00.a

PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000

PARAMETER C_NUM_BANKS_MEM = 1

PARAMETER C_MAX_MEM_WIDTH = 8

PARAMETER C_MEM0_WIDTH = 8

PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1

PARAMETER C_SYNCH_MEM_0 = 0

PARAMETER C_TCEDV_PS_MEM_0 = 110000

PARAMETER C_TWC_PS_MEM_0 = 110000

PARAMETER C_TAVDV_PS_MEM_0 = 110000

PARAMETER C_TWP_PS_MEM_0 = 70000

PARAMETER C_THZCE_PS_MEM_0 = 35000

PARAMETER C_TLZWE_PS_MEM_0 = 15000

PARAMETER C_MEM0_BASEADDR = 0x85000000

PARAMETER C_MEM0_HIGHADDR = 0x85ffffff

BUS_INTERFACE SPLB = mb_plb

PORT Mem_A = fpga_0_FLASH_Mem_A_split

PORT Mem_DQ = fpga_0_FLASH_Mem_DQ

PORT Mem_OEN = fpga_0_FLASH_Mem_OEN

PORT Mem_WEN = fpga_0_FLASH_Mem_WEN

PORT Mem_CEN = fpga_0_FLASH_Mem_CEN

PORT RdClk = sys_clk_s

END

BEGIN mpmc

PARAMETER INSTANCE = DDR_SDRAM

PARAMETER HW_VER = 4.02.a

PARAMETER C_NUM_PORTS = 1

PARAMETER C_MEM_PARTNO = MT46V16M16-6

PARAMETER C_SPECIAL_BOARD = S3E_STKIT

PARAMETER C_MEM_BANKADDR_WIDTH = 2

PARAMETER C_MEM_DATA_WIDTH = 16

PARAMETER C_MEM_DQS_WIDTH = 2

PARAMETER C_MEM_DM_WIDTH = 2

PARAMETER C_MEM_TYPE = DDR

PARAMETER C_PIM0_BASETYPE = 2

PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000

PARAMETER C_MPMC_BASEADDR = 0x86000000

PARAMETER C_MPMC_HIGHADDR = 0x87ffffff

PARAMETER C_SPLB0_NATIVE_DWIDTH = 32

BUS_INTERFACE SPLB0 = mb_plb

PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk

PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n

PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr

PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr

PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n

PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE

PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n

PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n

PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n

PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM

PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS

PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ

PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O

PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O

PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s

PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s

PORT MPMC_Rst = sys_periph_reset

END

BEGIN xps_ethernetlite

PARAMETER INSTANCE = Ethernet_MAC

PARAMETER HW_VER = 2.00.a

PARAMETER C_SPLB_CLK_PERIOD_PS = 20000

PARAMETER C_BASEADDR = 0x81000000

PARAMETER C_HIGHADDR = 0x8100ffff

BUS_INTERFACE SPLB = mb_plb

PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk

PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk

PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs

PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv

PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data

PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col

PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er

PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en

PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data

END

BEGIN util_bus_split

PARAMETER INSTANCE = FLASH_util_bus_split_0

PARAMETER HW_VER = 1.00.a

PARAMETER C_SIZE_IN = 32

PARAMETER C_LEFT_POS = 0

PARAMETER C_SPLIT = 8

PORT Sig = fpga_0_FLASH_Mem_A_split

PORT Out2 = fpga_0_FLASH_Mem_A

END

BEGIN clock_generator

PARAMETER INSTANCE = clock_generator_0

PARAMETER HW_VER = 2.01.a

PARAMETER C_EXT_RESET_HIGH = 1

PARAMETER C_CLKIN_FREQ = 50000000

PARAMETER C_CLKOUT0_FREQ = 50000000

PARAMETER C_CLKOUT0_BUF = TRUE

PARAMETER C_CLKOUT0_PHASE = 0

PARAMETER C_CLKOUT0_GROUP = NONE

PARAMETER C_CLKOUT1_FREQ = 100000000

PARAMETER C_CLKOUT1_BUF = TRUE

PARAMETER C_CLKOUT1_PHASE = 0

PARAMETER C_CLKOUT1_GROUP = DCM0

PARAMETER C_CLKOUT2_FREQ = 100000000

PARAMETER C_CLKOUT2_BUF = TRUE

PARAMETER C_CLKOUT2_PHASE = 90

PARAMETER C_CLKOUT2_GROUP = DCM0

PORT CLKOUT0 = sys_clk_s

PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s

PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s

PORT CLKIN = dcm_clk_s

PORT LOCKED = Dcm_all_locked

PORT RST = net_gnd

END

BEGIN mdm

PARAMETER INSTANCE = debug_module

PARAMETER HW_VER = 1.00.c

PARAMETER C_MB_DBG_PORTS = 1

PARAMETER C_USE_UART = 1

PARAMETER C_UART_WIDTH = 8

PARAMETER C_BASEADDR = 0x84400000

PARAMETER C_HIGHADDR = 0x8440ffff

BUS_INTERFACE SPLB = mb_plb

BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg

PORT Debug_SYS_Rst = Debug_SYS_Rst

END

BEGIN proc_sys_reset

PARAMETER INSTANCE = proc_sys_reset_0

PARAMETER HW_VER = 2.00.a

PARAMETER C_EXT_RESET_HIGH = 1

PORT Slowest_sync_clk = sys_clk_s

PORT Dcm_locked = Dcm_all_locked

PORT Ext_Reset_In = sys_rst_s

PORT MB_Reset = mb_reset

PORT Bus_Struct_Reset = sys_bus_reset

PORT MB_Debug_Sys_Rst = Debug_SYS_Rst

PORT Peripheral_Reset = sys_periph_reset

END

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Xilinx Employee
Xilinx Employee
13,811 Views
Registered: ‎08-02-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hello,

 

That is the correct one.

 

If you look at the section  DDR_SDRAM of MHS, DDR is interfaced using MPMC. The HDL of this core is in Verilog.

 

You can check trying the simulation by commenting out the DDR SDRAM core.

 

HTH

----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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Explorer
Explorer
11,496 Views
Registered: ‎06-25-2008

Re: PE Student Edition supports only a single HDL Error In Modelsim

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I couldn't figure out how to get the comment-out to work so I reran XPS and left out the DDR memory part and that worked.  Is there a way to get the memory interface to compile in VHDL?  When I compiled the memory I tried selecting only VHDL only but that didn't seem to work.  Or will I not be able to use some peripherals?

Thanks,

DeWayne

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Explorer
Explorer
11,484 Views
Registered: ‎08-14-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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The MPMC, which is the default memory controller as of EDK 9.x, is only available in mixed VHDL/Verilog. It's a shame, although I like Verilog better than VHDL, but I am in a similar boat as you since my company only has a license for the VHDL version of ModelSim.

 

Whenever I use a design that uses the MPMC, I have to 'simulate' the design by running it directly on hardware.

 

I don't know if 10.1 still has the old cores, but EDK 9.1 and 9.2 still had the old DDR memory cores available by enabling the deprecated cores. If that's the case, you may be able to use one of the OPB MCH DDR, and the old Microblaze that still has OPB support.

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Contributor
Contributor
8,893 Views
Registered: ‎06-13-2008

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hello everyone,

 

I met an error when I tried to "launch HDL Simulator" after I "Compile Simulation Libraries" successfully.   The errors are shown as follows:

 

----------------------------------------------------------

 

Generating simulator compile script ...
ERROR:EDK:2604 - Unable to locate the precompiled library microblaze_v7_20_a.
   The file

   D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_20_a\hdl\vhdl
   \microblaze_types_pkg.vhd is distributed by Xilinx encrypted and will not be
   read by any simulator. Please use compedklib to setup the EDK precompiled
   libraries and provide the path to them using the -E switch.
ERROR:EDK:1172 - Error while creating simulator compile script
make: *** [simulation/behavioral/system_setup.do] Error 1
Done!

 

----------------------------------------------------------

 

Can anyone give me a solution for this? Many thanks!

 

Regards,

tarzan

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Xilinx Employee
Xilinx Employee
8,875 Views
Registered: ‎08-07-2007

Re: PE Student Edition supports only a single HDL Error In Modelsim

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Hi DeWayne,

 

Disabling the mixed language simulation support in XPS should do the trick.

 

-XF

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