09-05-2019 07:58 PM
I'm new to Xilinx development and I'm currently working the barebone driver for AXI IIC IP on ZCU102. There is an example in https://xilinx.github.io/embeddedsw.github.io/iic/doc/html/api/example.html, but are there corrosponding design on the PL side? I have tried to guess the design but the interrupt is not handled properly. Thank you.
09-05-2019 11:39 PM
09-06-2019 12:42 AM
You have the output of the AXI Interrupt controller connected to the interrupt of the AXI I2C. If you wanted to use the interrupt controller (which in this case you dont as you would only need the axi interrupt controller here if yu needed more than 16 interrupts), then connect to the input intr port on the AXI Interript controller. (btw, all input ports are on the left, output ports on the right in IPI)
So, connect the AXI I2C to the Zynq irq directly. If you have more than one interrupt you can use a concat IP. There is also example code for the axi i2c here:
you can reference the example for the gpio for testing the interrupt:
09-06-2019 04:24 AM
The problem is that the example used Interupt Controller IP. If I connected the interrupt signal directly, I'll have to rewrite the code acoording to the AR mentioned by @sebo, right?
May I also ask if the interrupt is accessable from both APU and RPU?