I want to write a userlogic plb master .for that i searched a lot but iam unable to find .I gone through the documentation of PLB interface of vertex5 and xapp DEBUG PPC440.Iam unable to understand the master HDL.
My application is taking the input form the DDR and applying PLB data to PCORE(adder) and seening result throgh hyper terminal .
Hi, If you do not understand master HDL. One of the solution is: Find documentation for your version of plb_ipif. Read about IP master interface. Also there you'll find timing diagram for IP master read/write transaction. So, your task is, instead of using master HDL, create your own hdl, which will work according IP master transaction timing diagram.