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Visitor confuey
Visitor
5,247 Views
Registered: ‎07-29-2009

PPC440, EDK 11.4 - Unable to STOP Processor

I have been working on a system design in EDK 11.4 that uses a Virtex-5 FX200T on a custom PCB (from PLDA).  The system has a single PPC440.  After a lot of help, I got the PPC440MC_DDR2 and MPMC memory controllers working properly with my on-board DDR2 (used both memory controllers since I had two, independent banks of DDR2...the MPMC is interfacing directly to the PLB bus).

 

The next thing I wanted to do was add a plbv46_pcie bridge for PCIe communications.  I added the core into my design and configured it.  The .bit file was succesfully generated.  I downloaded the .bit file into my FPGA via JTAG and it completes with no problems.  However, when I try to connect to the PPC440 through XMD, I receive that "Unable to STOP processor," error now.  I am initializing the FPGA with just the bootloop.  The JTAG boundary scan seems to detect the device chain fine.

 

In an effort to isolate the issue, I began removing cores from my design.  I deleted the plbv46_pcie bridge I had just added, but the same problem occurred.  I then removed the PPC440MC_DDR2 and the MPMC, but the problem STILL occurred.  I am now down to basically just a PPC440 with BRAM and an RS232 peripheral.  I have pasted my .MHS file below.

 

As another check, I reloaded an older version of my system design (PPC440MC_DDR2 and MPMC setup right before I tried adding the plbv46_pcie bridge).  That design version still works properly, and I receive no errors from it.  This indicates to me that my PCB is functioning properly.

 

I have also gone over the UCF file several times, and did not see any errors in there.

 

Any ideas on things I should check or investigate?

 

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX_pin, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX_pin, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0


BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x001FFF00
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00E00000
 PARAMETER C_PPC440MC_CONTROL = 0xf850008f
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xfffe0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PARAMETER C_CLKOUT3_FREQ = 200000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 200000000
 PARAMETER C_CLKOUT4_PHASE = 90
 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT4_BUF = TRUE
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
 PORT CLKOUT1 = clk_200_0000MHzPLL0
 PORT CLKOUT2 = clk_400_0000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
 PORT CLKOUT3 = clk_200_0000MHzPLL0_ADJUST
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_AUX_RESET_HIGH = 0
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
END

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3 Replies
Adventurer
Adventurer
5,227 Views
Registered: ‎09-15-2008

Re: PPC440, EDK 11.4 - Unable to STOP Processor

Did you already check basic things like DCM locked or not in this configuration?

Anyway, I do not know if this can you help but please consider that in the past we had strange behaviour also with very simple design, like the one you're in trouble; we work with EDK 10.1 and we had to replace just the data2mem program (the one that update the BRAM with the processor software) with the old version provided with EDK 9.1.

Regards

 Mariano

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Visitor confuey
Visitor
5,206 Views
Registered: ‎07-29-2009

Re: PPC440, EDK 11.4 - Unable to STOP Processor

I seem to have gotten around this problem.  I believe it was an issue with the PERSTn pin.  I had that pin connected to the Aux_Reset_In on my reset module as suggested by the plbv46_pcie datasheet.  And then I tried to connect to the PPC using XMD while the board was NOT plugged into my host machine's PCIe slot.  This would leave the PERSTn pin unconnected and probably in an unknown state.  Oops.
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Contributor
Contributor
5,018 Views
Registered: ‎02-19-2009

Re: PPC440, EDK 11.4 - Unable to STOP Processor

Were you able to get your DDR2 SDRAM working. I have almost same type of board with FX200T. I am having hard time to get the DDR2 controller work with PPC440. Can you please share your XBD and UCF file. What were the problems that you had in bringing the DDR2 controller up. Please share and provide some insight.
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