I have created a Packet FIFO for SP601:
- 2048 deepth
- common clock
- block ram
As you can see my simulation, I am writing 2048 data at the input. When the data is 1024 I am writing a TLAST = '1' for one cycle.
After my 2048th data, the fifo's input ready goes to = '0'.
The fifo write port 's ready is always set to '1' (ready to write)
My problem is: I don't why the fifo is not writing in two scenarios:
1. When Tlast is asserted
2. When the fifo is full.