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Observer sumanthhv
Observer
12,112 Views
Registered: ‎07-28-2008

Par failing on EDK 11.4

Dear forum members,

 

I've designed a system on custom board using the spartan-6 lx45t device on EDK 11.4 using the base system builder. Following is the 

device utilization summary after map:

 


  
   Number of LOCed IOBs                  97 out of 97    100%
   Number of SLICEXs                      4521 out of 6822   66%
   Number of Slice Registers             15138 out of 54576  27%
   Number used as Flip Flops          15136
     
   Number of Slice LUTS                  25539 out of 27288  93%
   Number of Slice LUT-Flip Flop pairs   25636 out of 27288  93%

 

However, after PAR the following error is thrown and bit file is not generated.

***************************************************************************************************************************************************************

ERROR:Xflow - Program par returned error code 30. Aborting flow execution...
make:
*** [__xps/system_routed] Error 1

 

 

I also get the following warnings during PAR.

***************************************************************************************************************************************************************

WARNING:Par:288 - The signal mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/prioencdrOutput_pri<1> has no load.  PAR will not
   attempt to route this signal.
Starting Router
Wirelength Stats for nets on all pins. NumPins: 130211
Phase  1  : 136053 unrouted;      REAL time: 2 mins 3 secs
Phase  2  : 125020 unrouted;      REAL time: 2 mins 21 secs
Phase  3  : 86813 unrouted;      REAL time: 7 mins 13 secs
Phase  4  : 98510 unrouted; (Setup:5539693, Hold:6858, Component Switching Limit:0)     REAL time: 19 mins 11 secs

***************************************************************************************************************************************************************
WARNING:Route:441 - The router has detected a very high timing score (5469167) for this design. It is extremely unlikely the router will be
   able to meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
   completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
   isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
   implementation or synthesis of logic in the critical timing path. If you would prefer the router continue trying to meet timing and you
   are willing to accept a long run time set the option "-xe c" to override the present behavior.
  Intermediate status: 43159 unrouted;       REAL time: 49 mins 19 secs
  Intermediate status: 29897 unrouted;       REAL time: 1 hrs 19 mins 31 secs
Updating file: system.ncd with current partially routed design.

***************************************************************************************************************************************************************
WARNING:Route:543 - Because this design is experiencing congestion, we recommend you run SmartXplorer with the "Use built-in SmartXplorer
   strategies for Congestion Reduction" radio button enabled in Project Navigator. For command line users, please run SmartXplorer with the
   -cr switch. This will run algorithms designed to avoid logic congestion. For more information on how to run SmartXplorer, please see the
   ISE Help (Project Navigator Users) or the Command Line Tools Users Guide (Command Line Users).
Phase  5  : 27042 unrouted; (Setup:21963466, Hold:6858, Component Switching Limit:0)     REAL time: 1 hrs 30 mins 19 secs
Total REAL time to Router completion: 1 hrs 30 mins 19 secs
Total CPU time to Router completion: 1 hrs 29 mins 47 secs
 

***************************************************************************************************************************************************************

WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.
   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
   are set in the tools for timing closure.
   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.
   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.
Number of Timing Constraints that were not applied: 8

*************************************************************************************************************************************************************** 

WARNING:Par:100 - Design is not completely routed.


***************************************************************************************************************************************************************  WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

***************************************************************************************************************************************************************  

Total REAL time to PAR completion: 1 hrs 31 mins 3 secs
Total CPU time to PAR completion: 1 hrs 30 mins 24 secs
Peak Memory Usage:  553 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 5587 errors found.
Number of error messages: 0
Number of warning messages: 8
Number of info messages: 1
Writing design to file system.ncd
PAR done!
***************************************************************************************************************************************************************  

 

Few days back the same warnings were thrown, but the bit file got generated, and system behaved as expected. But, since then the RTL of custom

IP core has changed, but by a very small amount. Please let me know, if someone faced the same problem and is there any workaround for it.

 

Thanks in advance,

Sumanth.

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18 Replies
Historian
Historian
12,094 Views
Registered: ‎02-25-2008

Re: Par failing on EDK 11.4

Seems like you have waaaaaaaaay more combinatorial logic than registered logic.
----------------------------Yes, I do this for a living.
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Explorer
Explorer
12,052 Views
Registered: ‎01-09-2009

Re: Par failing on EDK 11.4

or you might have used too many Slices which makes the routing process impossble becasue there are not enough free slices to be used for routing.

use more registers to beark down long paths. You have plenty free Slice Registers.

Message Edited by aminfar1 on 02-13-2010 03:21 PM
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Explorer
Explorer
11,853 Views
Registered: ‎05-30-2008

Re: Par failing on EDK 11.4

I am using the same part and get the same error. I do not believe my design is unbalanced or too highly mapped. It seems very possible that this may be a Spartan-6 LX45 issue, especially considering there are no other forum post about this and any other parts. The fact that both of us have the same problem with the same part and nobody else seems to is suspicious.

 

 

Device Utilization Summary:

   Number of BSCANs                          2 out of 4      50%
   Number of BUFGs                          10 out of 16     62%
   Number of BUFIO2s                         3 out of 32      9%
   Number of BUFIO2FBs                       2 out of 32      6%
   Number of BUFPLLs                         2 out of 8      25%
   Number of BUFPLL_MCBs                     1 out of 4      25%
   Number of DCMs                            1 out of 8      12%
   Number of DSP48A1s                       18 out of 58     31%
   Number of ILOGIC2s                        5 out of 376     1%
   Number of External IOBs                  78 out of 218    35%
      Number of LOCed IOBs                  78 out of 78    100%

   Number of External IOBMs                 11 out of 109    10%
      Number of LOCed IOBMs                 11 out of 11    100%

   Number of External IOBSs                 11 out of 109    10%
      Number of LOCed IOBSs                 11 out of 11    100%

   Number of IODELAY2s                       8 out of 376     2%
   Number of IODRP2_MCBs                    22 out of 376     5%
   Number of ISERDES2s                       8 out of 376     2%
   Number of MCBs                            1 out of 2      50%
   Number of OLOGIC2s                       12 out of 376     3%
   Number of OSERDES2s                      50 out of 376    13%
   Number of PLL_ADVs                        3 out of 4      75%
   Number of RAMB16BWERs                    52 out of 116    44%
   Number of RAMB8BWERs                      5 out of 232     2%
   Number of SLICEXs                      4064 out of 6822   59%
      Number of LOCed SLICEXs                1 out of 4064    1%

   Number of Slice Registers             11875 out of 54576  21%
      Number used as Flip Flops          11863
      Number used as Latches                 5
      Number used as LatchThrus              7

   Number of Slice LUTS                  14334 out of 27288  52%
   Number of Slice LUT-Flip Flop pairs   14792 out of 27288  54%


Overall effort level (-ol):   High
Router effort level (-rl):    High 

 

 

 

 ...

 

 

ERROR:Xflow - Program par returned error code 30. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

Message Edited by thirdeye on 03-24-2010 09:28 AM
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Explorer
Explorer
11,818 Views
Registered: ‎01-09-2009

Re: Par failing on EDK 11.4

Interesting. Your report looks fine to me. Sometimes upgrading to a newer version helps. Try v11.5.
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Explorer
Explorer
11,806 Views
Registered: ‎05-30-2008

Re: Par failing on EDK 11.4

I tried after updating to 11.5 with the same result.

 

11.5 gave me an error that I did not receive in 11.4 about my clocking which allowed me to fix a problem I had. After fixing this I still get the same "error code 30".

 

I have a copy of the project with different clocking and it builds successfully so I am working with that now.

 

It would be nice if EDK would give some sort of useful error like "could not route design" or even better "could not route design because of ..."

 

I think it is my clocking resources that are having trouble being routed as opposed to slices or whatever. This is likely why changes to the clocking brought about a successful build.

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Explorer
Explorer
11,798 Views
Registered: ‎01-09-2009

Re: Par failing on EDK 11.4

Check all warnings in the synthesis and P&R processes. You might get some clues.

 

BTW, if you finally find the root of the problem, please post it. I am really eager to know.

 

aminfar

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Xilinx Employee
Xilinx Employee
11,726 Views
Registered: ‎08-07-2007

Re: Par failing on EDK 11.4

It sounds to me that PAR fails to meet timing and thus stops with error.

 

It's the default behavior of PAR and there's a way to override it to allow it generate a NCD file, so that you can perform a timing analysis with the NCD.

 

Try disabling the option in XPS Project Options -> Hierarchy and Flow -> Treat timing closure failure as an error.

 

-Felix

 

 

 

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Explorer
Explorer
11,718 Views
Registered: ‎05-30-2008

Re: Par failing on EDK 11.4

I do have "treat timing closure as an error" unchecked and yet still recieve the error. I opened a webcase that after a week still had no resolution. I changed the clocking in my design and I can now build it.

 

I am not so concerned about this error, but more with the fact that EDK provides a more or less useless error that gives no indication of the reason for the failure - making it very hard to debug. Only by trial and error could I get my system to build.

 

My webcase resulted in a filing of a change request for more useful error messages. It would be great if EDK would also provide more accessible options for different routing techniques, multiple passes, etc. Instead of increasing EDK's ability the options are decreasing over time.

 

I have been using EDK for years and I am still waiting for it to mature. I am also waiting for Windows 64 bit support for EDK.

0 Kudos
11,691 Views
Registered: ‎03-25-2010

Re: Par failing on EDK 11.4

I too see the error in 11.4, but I'm targetting an XC5VFX100T. I recieved the error after adding some TEMAC outputs to my already present chipscope ILA. The design built fine just prior to that and this is the only change I made and now receive the "Program par returned error code 30" error.

 

Can you elaborate on what clocking changes you made to fix it?

 

Thanks,

bryan

 

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Explorer
Explorer
8,514 Views
Registered: ‎05-30-2008

Re: Par failing on EDK 11.4

Bryan,

 

Unfortunately my clocking changes will not likely apply to your design. I think that EDK just has trouble routing in Spartan-6 still. You are not using  Spartan-6 so I guess that puts some holes in my argument - I guess EDK just has toruble routing - period.

 

I got around the problem and then in attempting to use Chipscope I encountered the same problem again. My co-worker building almost an identical design in ISE had no problem and has not recieved any "error code 30" in ISE. Of course he did not have a Microblaze, etc so this makes sense.

 

My design has the EDK clock_generator core taking in the input clock pin and driving the rest of the sytem with sys_clk_s. This sys_clk_s then was driving a PLL anda DCM that were then driving logic. I also had a 1.5x sys_clk driving logic and 2x driving the memory controller. The DCM generated 1x, 2x and 2x180. The PLL was also generating a 2x clk.

 

I changed the design so that clock_generator drives sys_clk and most logic. Sys_clk drives the PLL which makes a 2x and 2x180 clk which drive the other logic. The clock_generator also drives the memory clks (actually 4x sys_clk and not 2x as I thought they should be) and drives the 1.5x clk to some other logic.

 

So - kinda confusing, but basically I created simpler clock structure that eliminated some clock resources. I do not know that this in itself fixed the problem, but this somehow altered the routing enough for EDK to be able to route it all.

 

I would suggest opening a webcase about this so you can send them your project and they can look at your specific issues. I had a webcase that was somehwat unsuccessful as faras actually solving my problems, but resulted in a  Change request for EDK to provide useful errors that tell what the cause of the error is and not just "error code 30".

 

Sorry I cannot be of more help.

 

Chipscope is very useful, but I was unable to use it in this design successfully. Luckily my custom board had a handful of test points on unused pins so I was able to route signals out to test pins (because chipscope would not build without error) and I was able to debug my system using an oscilloscope. Chipscope is supposed to eliminate the need for this, but if you have test pins you may consider doing this.

 

I was at one pojnt able to use chipscope as long as I only probed signals that were not clocks, etc. It is all about the signals you choose to probe - I have had problems with this in the past. Most signals are fine, but certian ones like clocks or perhaps ones that are located farther away within the device will cause routing problems.

 

Good luck.

 

Josh

 

Message Edited by thirdeye on 04-12-2010 11:09 AM
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Explorer
Explorer
8,485 Views
Registered: ‎03-04-2010

Re: Par failing on EDK 11.4

I have just the same problem on my Virtex 4 FX (ML410) with EDK 10.1 SP3. Since I added the hard TEMAC and xps_ll_temac cores to my design, I get clocking errors while place and route.

Till now I've changed the projec options according to felix post and I've chosen SmartXplorer. Maybe it would help, but I'm not sure because it takes a long time running several iterations. Perhaps it might be useful to post the utilization summary

 

 

Device Utilization Summary:

Number of BUFGs 16 out of 32 50%
Number of DCM_ADVs 2 out of 12 16%
Number of EMACs 2 out of 2 100%
Number of GT11s 16 out of 16 100%
Number of LOCed GT11s 16 out of 16 100%

Number of IDELAYCTRLs 7 out of 20 35%
Number of LOCed IDELAYCTRLs 7 out of 7 100%

Number of ILOGICs 120 out of 576 20%
Number of External IOBs 261 out of 576 45%
Number of LOCed IOBs 238 out of 261 91%

Number of External IPADs 32 out of 620 5%
Number of LOCed IPADs 0 out of 32 0%

Number of JTAGPPCs 1 out of 1 100%
Number of OLOGICs 219 out of 576 38%
Number of External OPADs 32 out of 32 100%
Number of LOCed OPADs 0 out of 32 0%

Number of PPC405_ADVs 2 out of 2 100%
Number of RAMB16s 34 out of 232 14%
Number of Slices 9999 out of 25280 39%
Number of SLICEMs 216 out of 12640 1%



Overall effort level (-ol): High
Router effort level (-rl): High

Starting initial Timing Analysis. REAL time: 59 secs
Finished initial Timing Analysis. REAL time: 59 secs

 

 

 

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Explorer
Explorer
8,478 Views
Registered: ‎03-04-2010

Re: Par failing on EDK 11.4

Well, the SmartXplorer skript failed after the 7th run with the following message:

 

No runs succeeded. ERROR: Could not find BestRun in system_xplorer.rpt file. Possible reasons : 1. There were errors in ngdbuild. 2. There were timing errors. at E:/Xilinx/10.1/EDK/data/fpga_impl/edk_xplorer.pl line 128, <XPLORER_RPT> line 12. make: *** [__xps/system_routed] Error 2 Done!

 


 

0 Kudos
8,371 Views
Registered: ‎03-25-2010

Re: Par failing on EDK 11.4

Hi berufspenner,

 

Sorry for just now responding. I assumed I would get an email if this thread was updated, but I didn't. Anyways are you still having problems?

 

Out of curiousity, are you using a chipscope module to look at the temac signals? When I tried to do that is when I started seeing errors. I never did figure it out, just removed the temac from the chipscope module.

 

Try opening your clocking module in XPS and validating the clocks, sometimes this can find a wrong clock and correct it. Also try a newer version of XPS. I used 11.4.

 

Good luck

bryan

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Explorer
Explorer
8,350 Views
Registered: ‎03-04-2010

Re: Par failing on EDK 11.4

Hi bryan

 

thanks for your reply. Fortunately my personal problem has been solved. I've added the hard temac core but this wasn't necessary because the xps_ll_temac core would be enough. After dropping the "hard temac" core everything works fine till now.

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Visitor sunsocool
Visitor
7,201 Views
Registered: ‎06-26-2012

Re: Par failing on EDK 11.4

Windows 64bit can use  ISE now ,you can try version ISE13.4 or later.Now a new xilinx tool named vivado was able to use you can try that.,

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Highlighted
Explorer
Explorer
4,759 Views
Registered: ‎05-31-2015

Re: Par failing on EDK 11.4

Hi,

 

I am also having same error " Program par returned error code 30. Aborting flow execution..." in XPS now with spartan 6 XC6SLX45. Please can you elaborate on change in clocking you made or how else you solved it. Like you reduced clock frequency or something else....Thanks in advance.

 

Tags (2)
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Explorer
Explorer
4,741 Views
Registered: ‎05-30-2008

Re: Par failing on EDK 11.4


sha@hys wrote:

Hi,

 

I am also having same error " Program par returned error code 30. Aborting flow execution..." in XPS now with spartan 6 XC6SLX45. Please can you elaborate on change in clocking you made or how else you solved it. Like you reduced clock frequency or something else....Thanks in advance.

 


I do not recall this exact issue from 5 years ago, but I often get similar non-sensical errors from ISE/EDK. Often cleaning the project generated files will resolve these issues for me. At other times I have had to recreate a project and add my source files again and this has magically fixed errors that do not make sense. It is unclear to me how/why this happens. I now work primarily with ISE 14.7 and I still get similar behavior sometimes, but much less than in older versions.

 

Good Luck!

Josh

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Explorer
Explorer
4,718 Views
Registered: ‎05-31-2015

Re: Par failing on EDK 11.4

Thank you Josh..

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