UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
7,869 Views
Registered: ‎03-04-2015

Problem with AXI DMA

Hello,

I am using AXI DMA (v7.1) IP in my design with vivado 2014.4. I am trying to transfer data from FPGA to DDR and I have my custom IP in the design which sends stream data to DMA with 4 bytes in a data beat and DMA sends it on to MM DDR. I am using the DMA in simple DMA mode with only read channel enabled and I attached the configuration in the image file. I have a couple of problems.

 

(1) The s_axis_s2mm_tready of the DMA is going to zero after four beats of data. I am attaching the debug wave forms obtained in vivado. I obtained debug data for 1024 samples and tready does not reassert. 

 

(2) The documentation on DMA IP says and I quote "In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run much before the actual data arrives". I am wondering what does it mean by absence of setup. I am programming my DMA by writing to the s2mm regesters for receiving 2048 bytes of data but still DMA pulls down s_axis_s2mm_tready signal low.

 

The following is the tcl script for programming my DMA

 

mwr 0x40400030 0                                  
mwr 0x40400030 1                                 #Starting my DMA operation by changing LSB of control regester to 1 
mwr 0x40400048 0x1ff00000               #Writting destination address to destination address regester
mwr 0x43c00000 0xe                             #This command starts my IP to send random stream data
mwr 0x40400058 1024                          #Writing number of bytes into destination address regester

 

I am tightly following the programming sequence given in the documentation for the IP. Please somebody suggest me a reason for this. 

waveform.png
dma.png
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
7,840 Views
Registered: ‎08-02-2011

Re: Problem with AXI DMA

"In the absence of any setup " means when nothing has been programmed to the registers to kick off a transfer.

What's happening is that the DMA is accepting those 4 samples right out of reset because it comes up well before the processor has 'setup' the DMA. Then when the processor finally gets around to kicking off a transfer, the DMA will bring tready back up to start accepting the rest of the data.
www.xilinx.com
0 Kudos
Visitor mugilvanan
Visitor
1,150 Views
Registered: ‎10-12-2017

Re: Problem with AXI DMA

Hi, 

      The same setup in petalinux gives the same problem, tready is not going high at all. It is going high only when I run the same program again. I get the whole data which I should have gotten in the previous execution. This happens, if reset was not given each time. If reset is given then again after four clicks of data tready goes low. In your post, you mentioned about processor setup. Is there any setup program, which I can execute immediately after booting so that DMA works fine afterwards??

 

Thank you!!!

 

0 Kudos