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drbarryh
Visitor
Visitor
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Registered: ‎12-09-2019

Problem with AXI S2MM DMA and SDK

Hello XILINX Forum Experts

I have been having troiuble using the AXI DMA engine ins S2MM, simple transfer mode. 

What happens is when i start a transfer after doing register initialization for the DMA and interrupt system (as per the example design C code in xaxidma_example_simple_intr.c from Xilinx\Vivado\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_9\examples)  the transfer sometimes seems to run and work and other times it just fails and trashes the SDK and the only way to recover is by a SDK re start. Also i may have to reload the FPGA bitfile as well.

This is an interrupt driven DMA transfer from an AXIS FIFO through DMA to the DDR on a ZEDBOARD.

So when the transfer fails i pause the program (i am running in Debug Mode) and:by checking the DMA status register this error flag is set:  DMASlvErr

Occasionally i see this Error flag set : DMAIntErr but i think that maybe due to an illegal length being loaded into the length field.

 
The description of the DMASlvErr error is (from XILINX PG021 for the AXI DMA):
 
DMA Slave Error. This error occurs if the slave read from the
Memory Map interface issues a Slave Error. This error
condition causes the AXI DMA to halt gracefully. The
DMACR.RS bit is set to 0 and when the engine has completely
shut down the DMASR.Halted bit is set to 1.
• 0 = No DMA Slave Errors.
• 1 = DMA Slave Error detected.

 

When the transfer works and visualising the data through a memory window in the SDK i see that that start looks ok but then some data gets missed (set to 0) and then the data looks ok again, repeat until end of transfer window. I am trying to do around 1.3 Mbytes transfers. My DMA OP core has its length field se to 22 bits so that should theoretically allow up to 4 Mbytes. I also never seem to see the IOC flag being set in the DMA status register although i do get an RX Transfer Interrupt flag set.

Has anybody else seen this sort of behaviour using the AXIS DMA engine?

I am using VHDL and Vivado 2019.1 on a ZEDBOARD.

 

Thanks, Dr Barry H

 

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3 Replies
abommera
Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Hi @drbarryh ,

The AXI DMA slave error (DMASlvErr) is set, when any error response is received from AXI slave. So place the ILA on AXI slave port and observe the error conditions from BRESP signal. 

Thanks & Regards
Anil B
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drbarryh
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Registered: ‎12-09-2019

Hi Anil,

Thanks for the reply. I will try that and check the BRESP value coming backl from the AXI Slave. Is there an error code defintion anywahere i can use to evaluate what each error value actually means ?

Thanks, Dr Barry H

 

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@drbarryh 

Response codes are defined in the AXI4 specification.  They are:

2'b00: Okay

2'b01: EXOKAY (exclusive access okay, shouldn't get this with the S2MM core)

2'b10: SLVERR (slave error, comes from the slave per spec if the slave encounters an error)

2'b11: DECERR (decoder error, comes from the interconnect, although theoretically the slave could emit this it probably shouldn't.)

Let me double check what core you are connecting to, however.  If it is a user core, have you considered the possibility that the core might not be AXI4 standard compliant?

Dan

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