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2,891 Views
Registered: ‎03-25-2014

Problem with NPI writing in DDR2

Hi,

 

I need some help with reading and writing to the DDR2 memory with a npi.

 

I have 2 NPI connections, one to read from the memory and to write to the memory.

I have added the files from xps as attachement.

 

The idea is using sdk to check if I have written something in the memory and the check if I have read something from the memory.

 

Here is the code that I use in SDK.

int main()
{
    init_platform();
    xil_printf("\n\rHello world\n\r");

	while (1){

		*readLoc = 0xFFFF;
		*writeLoc = 0x0;
		xil_printf("read npi\n\r");
		xil_printf("Value readLoc: 0x%08X at memory loc: 0x%08X\n\r", *readLoc, readLoc);
		*ptr_rd_slv1 = 0xFFFFFFFF;//enable read
		xil_printf("Value ptr_rd_slv1: 0x%08X at memory loc: 0x%08X\n\r", *ptr_rd_slv1, ptr_rd_slv1);
		do{
			rd_done = *ptr_rd_slv3;
			xil_printf("Value done: 0x%08X\n\r", rd_done);
			}while (rd_done!=0x1);

		dataOut = *ptr_rd_slv2; //data that is read
		xil_printf("dataOut: 0x%08X at location: 0x%0BX\n\r", dataOut, ptr_rd_slv2);
		delay();

		xil_printf("write npi\n\r");
				*ptr_wr_slv3 = 0x0; //set the slave reg on 0 to check if it changed
				*ptr_wr_slv1 = 0xFFFFFFFF; //enable write

					do{
						wr_done = *ptr_wr_slv3;
						xil_printf("Value done: 0x%08X\n\r", wr_done);
						}while (wr_done!=1);

				xil_printf("data in loc: 0x%08X= 0x%08X\n\r",writeLoc,*writeLoc); // the data written in it should be F1F1F1F1
				delay();


	}

    return 0;
}

 

 

I have no idea where to start debugging, since I don't know if the error is in xps or sdk...

Can someone help me please?

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1 Reply
Highlighted
2,874 Views
Registered: ‎03-25-2014

Hey everyone,

 

I got my npi_write working but I still have problems with reading with npi.

 

can someone tell me if my fsm for the reading part is according to the timing diagram?

 

thanks in advance

 

process(old_state,Rd_en,AddrAck,RdFIFO_Empty,InitDone)
begin
	case old_state is	
	   when Startup =>if (InitDone = '1') then 
								next_state <= Idle;
							else
								next_state <= Startup;
							end if;
		when Idle	 =>if (Rd_en = '1')then
								next_state <= Rd_Addr_Req;
							else
								next_state <= Idle;
							end if;
		when Rd_Addr_Req => if(AddrAck = '1')then
								next_state <= RdFIFO_Not_Empty;
								else
								next_state <= Rd_Addr_Req;
								end if;
		when RdFIFO_Not_Empty => if(RdFIFO_Empty ='0')then
											case RdFIFO_Latency is
												when "00" => next_state <= Rd_Pop;
												when "01" => next_state <= Rd_Lat1_Pop;
												when "10" => next_state <= Rd_Lat2_Pop;
												when others => next_state <= RdFIFO_Not_Empty;
											end case;
										  else
											next_state <= RdFIFO_Not_Empty;
										 end if;
		when Rd_Pop => next_state <= idle;
		when Rd_Lat1_Pop => next_state <= Rd_Lat1_Data;
		when Rd_Lat1_Data => next_state <= idle;
		when Rd_Lat2_Pop => next_state <= Rd_Lat2_Wait;
		when Rd_Lat2_Wait => next_state <= Rd_Lat2_Data;
		when Rd_Lat2_Data => next_state <= idle;
		when others => next_state <=idle;
	end case;
end process;

process(Clk,Reset) --clk process
begin
	if (Reset = '1') then
		old_state <= Startup;
	elsif (Clk 'event and Clk = '1') then
		old_state <= next_state;
	end if;
end process;

process(old_state) -- transistion fsm
begin
	case old_state is
		when Startup =>AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done<='0';
							
		when idle => 	AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done<='0';
							
		when Rd_Addr_Req =>
							AddrReq<= '1';
							RdFIFO_Pop <= '0';
							Done<='0';
							
		when RdFIFO_Not_Empty =>
							AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done <='0';
							
		when Rd_Pop => 
							AddrReq<= '0';
							RdFIFO_Pop <= '1';
							Done<='1';
							
--							DataOutput(7 downto 0) <= RdFIFO_Data(31 downto 24);
--							DataOutput(15 downto 8) <= RdFIFO_Data(23 downto 16);
--							DataOutput(23 downto 16) <= RdFIFO_Data(15 downto 8);
--							DataOutput(31 downto 24) <= RdFIFO_Data(7 downto 0);	
							
		when Rd_Lat1_Pop =>
							AddrReq<= '0';
							RdFIFO_Pop <= '1';
							Done<='0';
							
		when Rd_Lat1_Data =>
							AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done<='1';
							
							
		when Rd_Lat2_Pop =>
							AddrReq<= '0';
							RdFIFO_Pop <= '1';
							Done<='0';
							
		when Rd_Lat2_Wait =>
							AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done<='0';								
									
		when Rd_Lat2_Data =>
							AddrReq<= '0';
							RdFIFO_Pop <= '1';
							Done<='1';
						
		when others =>							
							AddrReq<= '0';
							RdFIFO_Pop <= '0';
							Done<='0';	
	end case;
end process;

 

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