Question about importing architecture wizard generated DCM module

[bs0826]

Hi,

How could I put DCM module which is generate by architecture wizard into my XPS project? I tried to create a new IP in XPS and paste code in vhdl and usf files generated by wizrad into vhdl and usf files in XPS project. But I got

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ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:NgdBuild:981 - Could not find any associations for the following
   constraint:
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLK_FEEDBACK = 1X;>
   [system.ucf(582)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKDV_DIVIDE = 2.0;>
   [system.ucf(583)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKFX_DIVIDE = 31;>
   [system.ucf(584)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKFX_MULTIPLY = 7;>
   [system.ucf(585)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKIN_DIVIDE_BY_2 =
   FALSE;> [system.ucf(586)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKIN_PERIOD = 20.000;>
   [system.ucf(587)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKOUT_PHASE_SHIFT =
   NONE;> [system.ucf(588)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DESKEW_ADJUST =
   SYSTEM_SYNCHRONOUS;> [system.ucf(589)]: INST "DCM_SP_INST" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DFS_FREQUENCY_MODE =
   LOW;> [system.ucf(590)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DLL_FREQUENCY_MODE =
   LOW;> [system.ucf(591)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DUTY_CYCLE_CORRECTION =
   TRUE;> [system.ucf(592)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST FACTORY_JF = C080;>
   [system.ucf(593)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST PHASE_SHIFT = 0;>
   [system.ucf(594)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST STARTUP_WAIT = FALSE;>
   [system.ucf(595)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:NgdBuild:604 - logical block 'dcm_module_0/dcm_module_0' with type
   'dcm_module' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'dcm_module' is
   not supported in target 'spartan3e'.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:    29
  Number of warnings: 173

Total REAL time to NGDBUILD completion:  47 sec
Total CPU time to NGDBUILD completion:   46 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!


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I don't think it is the right way to do import files. Is there other way to import DCM module?

Thanks in advance.

Best,

[hgleamon1]

Use the Clock Generator IP in the XPS catalogue.

Regards,

Howard

[bs0826]

Thanks. But I need to have a 11.2908Mhz clock from spartan 3e starter kit.

[hgleamon1]

For Spartan 3 the clock generator instantiates a DCM to your specification. I don't understand the problem as you describe it. Why can't you use the IP?

Regards,

Howard

[bs0826]

---

@hgleamon1 wrote:

For Spartan 3 the clock generator instantiates a DCM to your specification. I don't understand the problem as you describe it. Why can't you use the IP?

Regards,

Howard

---

Hi hgleamon1,

I read data sheet again. Yes, clock generator  instantiates a DCM. But I can't find the wizard to use it. Could you tell me where to find it in ise 13.2?

Thanks.

Best,

[hgleamon1]

You are using XPS aren't you (at least you stated that in your first post)?

Personally, I find it easier to configure the IP directly rather than use the wizard but you can access the wizard from the Hardware toolbar menu:

 

Like I said, if you read the IP datasheet so you know what parameters mean what, you can go ahead and configure it directly like any other IP.

Regards,

Howard

[bs0826]

Hi hgleamon1,

Thank you.

I have tried the clock wizard. When I enter the desired frequency 11.2896 MHz in the drop down menu, there is a message popped out saying the frequency can't be generated. That's why I use dcm to manually select parameters M and D to systhesize the desired frequency.

May I ask how could I do it with clock generator? Thanks.

Best,

[hgleamon1]

When I enter the desired frequency 11.2896 MHz

This is not the same frequency as you mentioned in message 3 of this thread. Which one do you actually want? Must it be so accurate?

there is a message popped out saying the frequency can't be generated

What is your input frequency? Do you know that it is possible to generate your desired clock, with integer M and D?

May I ask how could I do it with clock generator?

I'll have to have a go myself and see what happens. Give me your input frequency and I'll play around a bit.

Regards,

Howard

[bs0826]

Thank you so much for helping.

I'm sorry foy the confusion. I tried to put different values int to the clock generator. 

If I put the value11.00MHz into fsl_i2s_0, the warning says "The frequency <11.000MHz> you entered can not be generated using the current reference clock. Please enter diffferent value", which means M and D are not used, riight?

Since the desired frequency is 11.2896 MHz. It can't be generated from 50MHz clock. Therefore, I use the approximated value 50*M/D=50*7/31=11.2903225806MHz and put the value into fsl_i2s_0. After clicking OK, The warning window shows "Please make sure the core specific logic for the following components is in sync with the system changing: proc_sys_reset_0, fsl_i2s_0, dcm_module_0". Does it mean I succefully generate 50*M/D=50*7/31=11.2903225806MHz?

[bs0826]

Forgot to say.

Why do I get "Please make sure the core specific logic for the following components is in sync with the system changing: proc_sys_reset_0, fsl_i2s_0, dcm_module_0"?

Thanks.

[hgleamon1 · Accepted solution]

What happens when you press "Validate Clocks" in the clock wizard?

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@bs0826 wrote:

Forgot to say.

Why do I get "Please make sure the core specific logic for the following components is in sync with the system changing: proc_sys_reset_0, fsl_i2s_0, dcm_module_0"?

Thanks.

---

If the clocks change, you need to ensure that the quoted modules are capable of handling the change. The system is just asking you to check. For example, the proc_sys_reset_0 may need to be connected to a different "Slowest_Sync_Clock" if you change clock frequencies (this is a hint - connect your slowest frequency to this port!).

The crucial test is - can you successfully validate the clocks? If yes, you're "home free" :)

Regards,

Howard

[bs0826]

After pressing Validate Clocks, it shows "validation was successful". 

Thank you for detailed explanation. :)