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hadii
Visitor
Visitor
8,621 Views
Registered: ‎11-10-2015

Reducing FPGA area with Microblaze and UARTs

Hi all,

 

I am trying to reduce the amount of area that the map program is reporting when using a microblaze processor along with many UARTs.

Specifically, I'm using a Spartan6LX25 with microblaze version 8.20.6 and the map report is giving the following report below. Essentailly about 83% of slice LUTs are being used, 12613/15032. Looking further down in the hierarchy report, it showed that the Microblaze was taking up 11261/15032 slices, the bulk majority of the slices. Approximately 5000 slices were taken up by 13 UARTs and the other 5000 slices were taken up by the microblaze itself. Does anyone have any suggestions how I can reduce the area of the design to allow for additional FPGA logic that is to be incorporated into the design without having to go to a larger part?

 

p.s. I have just recently tried to optimize the mapping procedure by doing the following:

-- using the "-bp" flag to map slice logic to block RAM

-- placer effort level set to "high"

-- combinatorial logic optimization flag turned on

-- global optimization set to 'area'

-- allow logic optimization across hierarchy

 

I am currently waiting for the results for the map procedure based on the above optimization changes.

 

Any help in dealing with this issue is appreciated.

 

Thanks.

 

"Slice Logic Utilization:
  Number of Slice Registers:                11,095 out of  30,064   36%
    Number used as Flip Flops:              11,076
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:               19
  Number of Slice LUTs:                     12,613 out of  15,032   83%
    Number used as logic:                   11,209 out of  15,032   74%
      Number using O6 output only:           7,730
      Number using O5 output only:           1,291
      Number using O5 and O6:                2,188
      Number used as ROM:                        0
    Number used as Memory:                     908 out of   3,664   24%
      Number used as Dual Port RAM:            176
        Number using O6 output only:            88
        Number using O5 output only:             2
        Number using O5 and O6:                 86
      Number used as Single Port RAM:            0
      Number used as Shift Register:           732
        Number using O6 output only:           215
        Number using O5 output only:             1
        Number using O5 and O6:                516
    Number used exclusively as route-thrus:    496
      Number with same-slice register load:    455
      Number with same-slice carry load:        41
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 3,755 out of   3,758   99%
  Nummber of MUXCYs used:                    2,832 out of   7,516   37%
  Number of LUT Flip Flop pairs used:       13,538
    Number with an unused Flip Flop:         3,621 out of  13,538   26%
    Number with an unused LUT:                 925 out of  13,538    6%
    Number of fully used LUT-FF pairs:       8,992 out of  13,538   66%
    Number of unique control sets:             659
    Number of slice register sites lost
      to control set restrictions:           2,398 out of  30,064    7%"

 

 

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5 Replies
htsvn
Xilinx Employee
Xilinx Employee
8,598 Views
Registered: ‎08-02-2007

hi,

 

you can change the optimization of the Microblaze IP by setting this parameter. PARAMETER C_AREA_OPTIMIZED = 1 in MHS

 

you can refer to the implementation strategies as shown in the link

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_imp_strategies.htm

 

--hs

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goran
Xilinx Employee
Xilinx Employee
8,593 Views
Registered: ‎08-06-2007

Hi,

 

MicroBlaze can only reach those utilization number if you maximize everything.

- What is the setting on MicroBlaze?

- How many UARTs do you use and how do you connect them to MicroBlaze?

- Are there any other peripherals?

 

Göran

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hadii
Visitor
Visitor
8,575 Views
Registered: ‎11-10-2015

Hi,

 

The microblaze settings selected from the configuration wizard were:

- enable debug

- use instruction and data caches

- enable exceptions

- use memory management

 

There are 13 UARTS and all are connected by PLB. Other peripherals are XPS timer.

 

Each UART uses about 413 LUTs. The microblaze wrapper uses 5563 LUTs. That accounts for 10932 LUTs of the 12901 LUTs that the microblaze uses. The microblaze wrapper uses 12 BRAMs.

 

Any suggestions to improve area usage is appreciated.

 

Thanks.

 

 

 

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hadii
Visitor
Visitor
8,572 Views
Registered: ‎11-10-2015

Hi,

 

Does setting the PARAMETER C_AREA_OPTIMIZED = 1 in MHS option mean that I cannot use the memory management unit (MMU)? I saw an option to adjust for reduced area in the microblaze wizard, but it mentioned that in addition to reduced throughput, the MMU would not be able to be used.

 

Thanks.

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goran
Xilinx Employee
Xilinx Employee
8,565 Views
Registered: ‎08-06-2007

Hi,

 

You can't have MMU and the area_optimized version of MicroBlaze.

 

Göran

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