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Observer
Observer
1,285 Views
Registered: ‎04-17-2018

[Reference Design-Matlab] Define and Register Custom Board- Error in Step 4.4

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Hi, I have defined and have registered a custom Board as a reference design metho:

https://it.mathworks.com/help/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html

The hardware is developed in Vivado Xilinx.

Only the last step 4.4 fails!

The step 4.3 works and gives me the following log:

Task "Build FPGA Bitstream" successful. Generated logfile: hdl_prj\hdlsrc\schema_1\workflow_task_BuildFPGABitstream.log Running embedded system build outside MATLAB. Please check external shell for system build progress. The generated bitstream file is located at: hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top_wrapper.bit Generate an HDL Workflow Command-Line Interface script to program the target device: hdlworkflow_ProgramTargetDevice.m.

While the step 4.4 doesn't work and give me the following problem

Failed Program target FPGA device. Task "Program Target Device" unsuccessful. See log for details. Generated logfile: hdl_prj\hdlsrc\schema_1\workflow_task_ProgramTargetDevice.log Downloading target FPGA device configuration over Ethernet to SD card ... Cannot identify hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top_wrapper.bit. No such file or directory.

I note that in the step 4.3 the file system_top_wrapper.bit is present in the directory, while in the step 4.4 the file disappeares! What is the problem? Can you help me? Thank thank thank you.

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Observer
Observer
1,377 Views
Registered: ‎04-17-2018

I have solved the problem. I create the bitstream in step 4.4. without  'run build externally'.

Thank yoiu

View solution in original post

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Observer
Observer
1,236 Views
Registered: ‎04-17-2018

a solution?

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Observer
Observer
1,208 Views
Registered: ‎04-17-2018

news?

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Observer
Observer
1,170 Views
Registered: ‎04-17-2018

can someone help me? thanks thanks

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Xilinx Employee
Xilinx Employee
1,134 Views
Registered: ‎10-06-2016

Hi @jackn,

 

I just review/check the link you are referencing and there is no point 4.4, so not sure on which step are you having issues. It seems that it might be within the HDL workflow Advisor window, but it's not clear, could you provide more info on this?

 

Regards

Ibai


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Observer
Observer
1,378 Views
Registered: ‎04-17-2018

I have solved the problem. I create the bitstream in step 4.4. without  'run build externally'.

Thank yoiu

View solution in original post

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