Resuming Zynq Ultrascale+ over JTAG

[djupdal]

This question is about doing invasive debugging over JTAG by accessing the external debug interface of the cortex a53 cores. 

After a breakpoint, I try to resume the Zynq ultrascale+. I understand I need to use the cross trigger interface in order to resume, so I do the following:

CTIGATE = 0 (no triggers are sent to other cores)
CTIOUTEN1 = 2 (forward channel 1 triggers to the CPU restart trigger event)
CTIAPPPULSE =  2 (trigger the event on channel 1)

This does, however, not resume the core. After doing the above, I read the PRSR register to be 0x811 and SRC.status to be 7 (breakpoint). So still halted. 

Is there anything wrong with the register settings above? Anything else I need to do to resume a core after a breakpoint?

Best regards, 

Asbjørn Djupdal

[arpansur]

Hi @djupdal,

Are you using the correct set of the settings needed for cross trigger?

You can go through http://www.wiki.xilinx.com/ZCU102+Cross+Trigger+Debug for sample design and see if you are missing something here.

[djupdal]

Thanks. 

But I am not sure this can be used in my case. I am using a custom device to control the JTAG of the Zynq and need to know how to resume the A53 core by writing to the external debug registers. So no Xilinx software is involved here. 

In other words, I want to implement the functionality of the "con" command in XSCT, but using my own software for writing to the JTAG port. I am not using the Xilinx developer tools for this. 

Thinking about it, this question may not be Zynq specific.  Maybe it would be more appropriate to find a more generic ARM forum. 

[sadanan · Accepted solution]

Here's some pseudo code

read(cti_addr + 0x0a0, &trig_out0);
read(cti_addr + 0x0a4, &trig_out1);
read(cti_addr + 0x140, &cti_gate);

/* Close CTI Gate */
write(cti_addr + 0x140, cti_gate & ~(uint32_t)1);

/* Enable CTI */
write(cti_addr + 0x000, 1);

/* Disable Channel 0 -> Trigger Out 0 */
write(cti_addr + 0x0a0, trig_out0 & ~(uint32_t)1);

/* Clear Channel 0 */
write(cti_addr + 0x018, 1);

/* Acknowlege Trigger Out 0 */
write(cti_addr + 0x010, 1);

/* Enable Channel 0 -> Trigger Out 1 */
write(cti_addr + 0x0a4, trig_out1 | 1);

/* Pulse Channel 0 */
write(cti_addr + 0x01c, 1);

/* Poll until restarted */
while (...) {
    if (read(dbg_addr + 0x88, &dscr) & 2) break;
}

[djupdal]

Thank you, sadanan. 

Based on the docs, I think your code is correct (except the test at the end that should check all status bits, not just bit 2). 

I have tried your code, and variants of it and still don't get it to work, so my guess is that some other setup must be done prior to this.

[djupdal]

Sadanan: I have marked your post as the solution to my problem.

I still mysteriously can't resume if the breakpoint is set earlier by the XSCT tool and I use my own custom jtag device to resume, but when I set breakpoints with my own tool, resume works using your code.  This is OK for me.  It nags me to not understand what the XSCT tool does differently, but it does not matter for my application. 

Thank you

[sadanan]

Hi,

To get past triggered breakpoints, you need to disable the breakpoint, single step past that instruction, re-plant the breakpoint and then resume. If you directly try to resume from the triggered breakpoint address, the breakpoint will be triggered again, making resume appear like it's not working at all