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Observer mkaspare
Observer
4,125 Views
Registered: ‎03-11-2014

SDK Generate Bitstream

Hello,

I try to implement XAPP1026 on my SP605.

I open the sw folder as explained in the pdf. Than I want to download system.bit and the system_bd.bmm files. But the system.bit cant be found.

I cleaned and rebuild the project but the console says that for target "all" nothing is to do.

Does anyone know what I am doing wrong?

 

Thank you

Screenshot.png
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6 Replies
Xilinx Employee
Xilinx Employee
4,120 Views
Registered: ‎08-02-2007

Re: SDK Generate Bitstream

Hi

 

Can you confirm if the hw_platform folder has been imported in the step2 of XAPP1026?

 

--Hem

 

 

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Observer mkaspare
Observer
4,111 Views
Registered: ‎03-11-2014

Re: SDK Generate Bitstream

Hello htsvn,

 

I have skipped step 2 because it is only for ZYNQ devices. But I have the SP605 with a Spartan 6.

So I import the folders in step 3. As you can see in my screenshot, the hardware folder is also imported.

 

Thanks for your support!

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Scholar stephenm
Scholar
4,099 Views
Registered: ‎05-06-2012

Re: SDK Generate Bitstream

you can just use the download.bit file in the xapp1026 zipped folder instead

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Xilinx Employee
Xilinx Employee
4,095 Views
Registered: ‎08-02-2007

Re: SDK Generate Bitstream

Hi,

 

It looks that we have to implment the design given in XAPP to generate the bitstream.

 

I just did a search of the *.bit in the complete XAPP and i could only find bitstreams in ready_to_download folder.

 

So at the moment you can try either to implement the design or use the files available in ready_to_download folder.

 

--Hem

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Scholar stephenm
Scholar
4,091 Views
Registered: ‎05-06-2012

Re: SDK Generate Bitstream

Import the download.bit into the hw_platform folder and use this instead. This will function just the same
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Observer mkaspare
Observer
4,085 Views
Registered: ‎03-11-2014

Re: SDK Generate Bitstream

Hello stephenm,

 

it works with the download.bit. But I want erase the webserver so that I do not have to use the DDR Memory. I only want use FPGA internal memory, so I think I have to make changes in the project.

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