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Adventurer
Adventurer
869 Views
Registered: ‎02-07-2014

SDK: Loading Program Error at Debug

Hi, 

 

I designed MicroBlaze and my logic in KCU105.  When I started a debug with SDK 2018.3, I got the error shown in the attached file.  My HDF is also attached here.  Vivado is also 2018.3.

 

Coud you let me know how I can fix it?

 

Best regards,

Koji

Capture.PNG
HDF.PNG
15 Replies
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Moderator
Moderator
822 Views
Registered: ‎03-25-2019

Hi Koji (@lsikiyota),

Could you please share your HDF file, so I could take a closer look on the issue.

Best regards,
Abdallah
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Adventurer
Adventurer
816 Views
Registered: ‎02-07-2014

Hi, Abdallah,

 

I uploaded my HDF here.  Apprecoiate your help!

 

To make sure my debug system on Windows 10, I built MicroBlaze example design in Vivado.  Then I confirmed Hellow World project worked.  So I think my MicroBlaze design in Block Design may have a problem.

 

Best regards,

Koji

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Moderator
Moderator
811 Views
Registered: ‎03-25-2019

Hi Koji (@lsikiyota),

You are welcome.
The hdf file you have provided doesn't include a bitstream. Could you please share the full one?

Best regards,
Abdallah
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Adventurer
Adventurer
806 Views
Registered: ‎02-07-2014

Hi, Abdallah,

Sure.  Here it is.

Regards,

Koji

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Moderator
Moderator
793 Views
Registered: ‎03-25-2019

HI Koji (@lsikiyota),

Thanks for the file, now I can reproduce the issue.

When connecting to the target, I get the following warning:
freq_warning.png
(Maybe you are not getting this because you have already checked the "Do not show this warning again" box.)

And the real reason behind the error you have reported was the use of this "bad" high JTAG frequency.
So, to fix the issue you should reduce the JTAG frequency as the following:

jtag_freq.png

Best regards,
Abdallah
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Adventurer
Adventurer
784 Views
Registered: ‎02-07-2014

Hi, Abdallah,

 

Do you mean that in case you changed JTAG clock to slower one, you didn't get the error?

 

In my case, I set JTAG clock frequency as 10MHz and could load bit file successfully.  Even after that, I got this error.

 

Regards,

Koji

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Moderator
Moderator
779 Views
Registered: ‎03-25-2019

Hi Koji (@lsikiyota),

Please try with 5MHz and let me know the results.

Best regards,
Abdallah
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Adventurer
Adventurer
771 Views
Registered: ‎02-07-2014

Hi, Abdallah,

 

Sure, I'll try it later.

 

And I changed MicroBlaze configuration by referring to Xilinx example deisgn.  After that, this problem was gone now.  However, I should understand root causes anyway.

 

Regards,

Koji

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Adventurer
Adventurer
764 Views
Registered: ‎02-07-2014

Abdallah,

 

In my previous case with JTAG clock=10MHz, it works with JTAG clock=5MHz, but doesn't work with 7.5MHz.

 

In my latest configuration update in MicroBlaze, it works with JTAG clock=10MHz.

 

Any idea what the root causes are?

 

Regards,

Koji

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Moderator
Moderator
754 Views
Registered: ‎03-25-2019

Hi Koji (@lsikiyota),

Happy that it has worked for you.

It's hard to say as I don't know what kind of changes you have made in your last update.

Best regards,
Abdallah
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Adventurer
Adventurer
750 Views
Registered: ‎02-07-2014

Hi, Abdallah,

 

My changes in MicroBlaze were listed below.

 

  1. Predefined Configurations from Microcontroller Preset to Current Settings.
  2. Enable Barrel Shifter was unchecked.
  3. Enable Additional Machine Status Register Instructions was unchecked.
  4. Enable Pattern Comparatoer was unchecked.
  5. Enable Reversed Load/Store and Swap Instructions was checked.
  6. Select implementation optimization from AREA to PERFORMANCE.

 

Any idea?

 

Regards,

Koji

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Moderator
Moderator
710 Views
Registered: ‎03-25-2019

Hi Koji (@lsikiyota),

Is this the failing scenario or the working one?
Acually, I need to know what change have you made from the failing scenario to the working one?

Best regards,
Abdallah
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Adventurer
Adventurer
704 Views
Registered: ‎02-07-2014

My list shows the changes from bad case to good one.

 

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Moderator
Moderator
694 Views
Registered: ‎09-12-2007

Instruction overrun means that the debugger has inserted an instruction that has not been completed when trying to add next instruction. Increasing the jtag freq would have helped here. However, you could have an underlying memory issue. 

 

Where are you executing from? DDR or BRAM? What is the clocking structure here?

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Adventurer
Adventurer
456 Views
Registered: ‎02-07-2014

Stephenm,

 

My code is loaded into SRAM(BRAM?) and executed from there.  

 

What do you mean about the clock structure?  I'm using KCU-105 and utilizing the clock source on PCBA to FPGA.

 

Regards,

Koji 

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