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Observer
Observer
1,034 Views
Registered: ‎03-07-2011

SDK Xilinx System Debugger and double Microblaze meaning

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Hi all,

I've moved a Microblaze based design made originally with VIVADO 2016.1 in VIVADO 2017.4, all the imported process was fine, updating IP and so on.

 

I've exported the hardware design with bitstream and then run the SDK.

 

I'm able to debug with the GDB debugger and also with the Xilinx System Debugger (with this one in 2016.1 was not) but I don't know why or what is means into the Xilinx System Debugger about another Microblaze indication with no clock. In my design I've only one Microblaze, where came from the second one?

 

whatis.jpg

Thank!

 

Best regards

 

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Xilinx Employee
Xilinx Employee
1,281 Views
Registered: ‎10-21-2010

Hi,

System debugger reads the MDM configuration register to determine how many instances of MB exist in the design. In your block design, there is only one MB, but the MDM seems to have 2 debug ports (MBDEBUG_0, 1). Due to this, MDM configuration register could be reporting 2 instances of MB. Can you try to get rid of the unused debug port in MDM, and generate a new bitstream?

 

You will not see this problem with GDB debugger in SDK, since it will always connect to only one MB at time, and your case it would connect to MB #0, since that what SDK sees in the HDF exported from Vivado

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Observer
Observer
1,009 Views
Registered: ‎03-07-2011

Here attached a pdf of the Block Design I'm unable to see two Microblaze in it... could you please guide me what I've to do now?

 

Also into the GDB debugger I can't see same issue...

 

gdb-dbg.jpg

 

Thanks

 

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Xilinx Employee
Xilinx Employee
1,282 Views
Registered: ‎10-21-2010

Hi,

System debugger reads the MDM configuration register to determine how many instances of MB exist in the design. In your block design, there is only one MB, but the MDM seems to have 2 debug ports (MBDEBUG_0, 1). Due to this, MDM configuration register could be reporting 2 instances of MB. Can you try to get rid of the unused debug port in MDM, and generate a new bitstream?

 

You will not see this problem with GDB debugger in SDK, since it will always connect to only one MB at time, and your case it would connect to MB #0, since that what SDK sees in the HDF exported from Vivado

View solution in original post

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Observer
Observer
992 Views
Registered: ‎03-07-2011

Hi @sadanan,

thank you very much this solve the issue.

 

The debugger module was set for 2 Microblaze, reduced to 1 into the Block Design, then I've regenerated the bitstream.

 

After that I've exported the Hardware with bitstream and then start the SDK.

 

Now I've do the debug configuration and in this one I've to force program FPGA, without this we see two Microblaze, by checking this option the Xilinx System Debugger was able to show only one Microblaze.

 

xsysdbg-ok.jpg

to stop the simulation I use first "disconnect" and then "terminate and remove" is the correct sequence?

 

Here below my configuration for the Xilinx System Debugger.

 

sys-dbg-cfg1.jpg

 

sys-dbg-cfg2.jpg

 

from your perpective is all correct?

 

Thanks again!!

 

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Xilinx Employee
Xilinx Employee
983 Views
Registered: ‎10-21-2010

Hi,

If you have programmed the new bitstream before launching the debug from SDK, then you wouldn't have to force 'program FPGA' in debug configuration.

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