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Registered: ‎01-18-2012

SP605 EDK System Simulation - DDR3 memory initialization problem

I am testing SP605 board EDK System Simulation using Modelsim.
The board is using Micron MT41J64M16LA-187E DDR3 SDRAM.
I tried to find similar project from the Xilinx web-site. XAPP1003 and XAPP1111 have the EDK System Simulation examples. But as you know they are quite old versions and it was not proper for the SP605 board.
I could not find the proper DRAM simulation model for MT41J64M16LA-187E DDR3 SDRAM from Micron web-site therefore I generated the model using MIG Coregen tool and copied to my System Simulation Folder.
From my test bench, I tried DRAM memory initialization but it happened memory copy size error like below two questions. I tried MAX_MEM mode and Non-MAX_MEM mode both and finally I have manually changed MEM_SIZE and I passed the memory copy steps.


I tried the memory copy like XAPP1003 like below code. The SP605 board only has one DDR memory and I modified it.
But on my simulation I couldn't get the proper DRAM read value and the read data value was All "XXXX".

I have tried DDR1 SDRAM using same code and same board configuration and only have changed MPMC options and Simultion model for DDR1 memory. But the simulation was successful. I could execute my SDK software code on my Modelsim simulation.
I think my current problem is DDR3-SDRAM initialization problem and the simulation model structure of DDR3 was a bit different from DDR1.

Does anyone have experiences of DDR3-SDRAM initialization for EDK System Simulation on Modelsim?
I have spent lots of time and now I am very frustrated.
Any advices and tips will be much appreciated.


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