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Participant amoralesv
Participant
1,660 Views
Registered: ‎01-21-2011

SYS_Rst on FSL does not flush FSL

Hi all,

I'm working in a Partial Reconfiguration project with Microblaze, Hard Ethernet, GPIO, DDR SDRAM, HW ICAP, FSL (v2.11.c), RS-232 Uart, etc, for ML509. The Microblaze is connected to a custom interface created in XPS (as a local Pcore), via FSL FIFOs (in asynch mode, even though I use the same clock signal). The 1st FSL is used to send data from Microblaze to a custom HW receiver out of XPS (in ISE). The 2nd FSL receives data via custom interface from custom HW producer out of XPS (different versions via downloading partial bitstream). I also built Linux 2.6.37 on Microblaze.

My problem is that I cannot flush the FSL using SYS_Rst pin. SYS_Rst (active HIGH according to parameter C_EXT_RESET_HIGH=1, document DS449) is connected to one output of GPIO. Everything seems to be well connected. I'm able to run a C application to perform Partial Reconfiguration of HW producer (up and down counter PR module versions that sends data to FSL and printf on console). After sending data to FSL, I want to flush the FSL, but it seems that SYS_Rst does not work, even though I drive SYS_Rst =1 via GPIO (even for 1 second, I tried also with '0' and it doesn't work), so next time I run the C application, there is still some data from previous run. I assume that SYS_Rst will flush the FSL. Is there anything that I'm missing?


Here are the relevent parts of my design.

The system.mhs:

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.4 Build EDK_MS4.81d
# Sun Oct 30 18:26:44 2011
# Target Board:  Xilinx XUPV5-LX110T Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vlx110t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 100.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0

 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin, DIR = IO
 PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin = fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
 PORT xps_gpio_0_GPIO_IO_O_pin = xps_gpio_0_GPIO_IO_O, DIR = O, VEC = [0:31]
 PORT interface_0_Rst_pin = interface_0_Rst, DIR = I
 PORT interface_0_consumer_to_microblaze_rdy_pin = interface_0_consumer_to_microblaze_rdy, DIR = I
 PORT interface_0_microblaze_to_consumer_wr_en_pin = interface_0_microblaze_to_consumer_wr_en, DIR = O
 PORT interface_0_microblaze_to_consumer_data_pin = interface_0_microblaze_to_consumer_data, DIR = O, VEC = [0:31]
 PORT interface_0_producer_to_microblaze_rdy_pin = interface_0_producer_to_microblaze_rdy, DIR = I
 PORT interface_0_microblaze_to_producer_rd_en_pin = interface_0_microblaze_to_producer_rd_en, DIR = O
 PORT interface_0_producer_to_microblaze_data_pin = interface_0_producer_to_microblaze_data, DIR = I, VEC = [0:31]
 PORT clock_generator_0_CLKOUT0_pin = clk_100_0000MHzPLL0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
 PORT clock_generator_0_CLKOUT1_pin = clk_125_0000MHz, DIR = O, SIGIS = CLK, CLK_FREQ = 125000000
 PORT Hard_Ethernet_MAC_GTX_CLK_0_pin = clk_125_0000MHz_in, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0x50000000
 PARAMETER C_ICACHE_HIGHADDR = 0x5fffffff
 PARAMETER C_CACHE_BYTE_SIZE = 16384
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0x50000000
 PARAMETER C_DCACHE_HIGHADDR = 0x5fffffff
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER HW_VER = 8.00.b
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_FSL_LINKS = 1
 PARAMETER C_PVR = 2
 PARAMETER C_USE_MMU = 3
 PARAMETER C_MMU_ZONES = 2
 PARAMETER C_ICACHE_LINE_LEN = 8
 PARAMETER C_ICACHE_STREAMS = 1
 PARAMETER C_ICACHE_VICTIMS = 8
 PARAMETER C_DIV_ZERO_EXCEPTION = 1
 PARAMETER C_DPLB_BUS_EXCEPTION = 1
 PARAMETER C_IPLB_BUS_EXCEPTION = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_OPCODE_0x0_ILLEGAL = 1
 PARAMETER C_USE_HW_MUL = 2
 PARAMETER C_USE_DIV = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE SFSL0 = interface_0_to_microblaze_0
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE MFSL0 = microblaze_0_to_interface_0
 PORT MB_RESET = mb_reset
 PORT INTERRUPT = microblaze_0_Interrupt
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_interface_0
 PARAMETER HW_VER = 2.11.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_IMPL_STYLE = 1
 PARAMETER C_FSL_DEPTH = 512
 PARAMETER C_USE_CONTROL = 0
 PARAMETER C_ASYNC_CLKS = 1
 PORT FSL_Clk = clk_100_0000MHzPLL0
 PORT FSL_M_Clk = clk_100_0000MHzPLL0
 PORT FSL_S_Clk = clk_100_0000MHzPLL0
 PORT SYS_Rst = interface_0_Rst
 PORT FSL_Rst = microblaze_0_to_interface_0_FSL_Rst
END

BEGIN fsl_v20
 PARAMETER INSTANCE = interface_0_to_microblaze_0
 PARAMETER HW_VER = 2.11.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_IMPL_STYLE = 1
 PARAMETER C_FSL_DEPTH = 512
 PARAMETER C_USE_CONTROL = 0
 PARAMETER C_ASYNC_CLKS = 1
 PORT FSL_Clk = clk_100_0000MHzPLL0
 PORT FSL_M_Clk = clk_100_0000MHzPLL0
 PORT FSL_S_Clk = clk_100_0000MHzPLL0
 PORT SYS_Rst = interface_0_Rst
 PORT FSL_Rst = interface_0_to_microblaze_0_FSL_Rst
END

BEGIN interface
 PARAMETER INSTANCE = interface_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = microblaze_0_to_interface_0
 BUS_INTERFACE MFSL = interface_0_to_microblaze_0
 PORT FSL_S_Rst = microblaze_0_to_interface_0_FSL_Rst
 PORT FSL_M_Rst = interface_0_to_microblaze_0_FSL_Rst
 PORT consumer_to_microblaze_rdy = interface_0_consumer_to_microblaze_rdy
 PORT microblaze_to_consumer_wr_en = interface_0_microblaze_to_consumer_wr_en
 PORT microblaze_to_consumer_data = interface_0_microblaze_to_consumer_data
 PORT producer_to_microblaze_rdy = interface_0_producer_to_microblaze_rdy
 PORT microblaze_to_producer_rd_en = interface_0_microblaze_to_producer_rd_en
 PORT producer_to_microblaze_data = interface_0_producer_to_microblaze_data
 PORT Rst = interface_0_Rst
 PORT Clk = clk_100_0000MHzPLL0
END

BEGIN xps_gpio
 PARAMETER INSTANCE = xps_gpio_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_O = xps_gpio_0_GPIO_IO_O
END

Here are the relevant parts of top.vhd (top of hierarchy):
...
...
architecture Behavioral of top is
    component system
    port(
        fpga_0_clk_1_sys_clk_pin                     : in    std_logic;
        fpga_0_rst_1_sys_rst_pin                     : in    std_logic;
        fpga_0_RS232_Uart_1_RX_pin                   : in    std_logic;
        fpga_0_RS232_Uart_1_TX_pin                   : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin  : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin    : in    std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin      : out   std_logic_vector(7  downto 0);
        fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin    : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin    : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin   : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin      : in    std_logic_vector(7  downto 0);
        fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin    : in    std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin    : in    std_logic;
        fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin   : in    std_logic;
        fpga_0_Hard_Ethernet_MAC_MDC_0_pin           : out   std_logic;
        fpga_0_Hard_Ethernet_MAC_MDIO_0_pin          : inout std_logic;
        fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin     : in    std_logic;
        fpga_0_DDR2_SDRAM_DDR2_Clk_pin               : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin             : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CE_pin                : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CS_n_pin              : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_ODT_pin               : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin             : out   std_logic;
        fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin             : out   std_logic;
        fpga_0_DDR2_SDRAM_DDR2_WE_n_pin              : out   std_logic;
        fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin          : out   std_logic_vector(1  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_Addr_pin              : out   std_logic_vector(12 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQ_pin                : inout std_logic_vector(63 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DM_pin                : out   std_logic_vector(7  downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_pin               : inout std_logic_vector(7 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin             : inout std_logic_vector(7 downto 0);
        fpga_0_SysACE_CompactFlash_SysACE_CLK_pin    : in    std_logic;
        fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin  : in    std_logic;
        fpga_0_SysACE_CompactFlash_SysACE_MPD_pin    : inout std_logic_vector(15 downto 0);
        fpga_0_SysACE_CompactFlash_SysACE_MPA_pin    : out   std_logic_vector(6 downto 0);
        fpga_0_SysACE_CompactFlash_SysACE_CEN_pin    : out   std_logic;
        fpga_0_SysACE_CompactFlash_SysACE_OEN_pin    : out   std_logic;
        fpga_0_SysACE_CompactFlash_SysACE_WEN_pin    : out   std_logic;
        xps_gpio_0_GPIO_IO_O_pin                     : out   std_logic_vector(0 to 31);
        clock_generator_0_CLKOUT1_pin                : out   std_logic;
        Hard_Ethernet_MAC_GTX_CLK_0_pin              : in    std_logic;

        interface_0_Rst_pin                          : in    std_logic;
        -- Control and data signals between MicroBlaze and custom HW consumer (consumer.vhd)
        interface_0_consumer_to_microblaze_rdy_pin   : in    std_logic;
        interface_0_microblaze_to_consumer_wr_en_pin : out   std_logic;
        interface_0_microblaze_to_consumer_data_pin  : out   std_logic_vector(0 to 31);

        -- Control and data signals between MicroBlaze and custom HW producer (producer.vhd)
        interface_0_producer_to_microblaze_rdy_pin   : in    std_logic;
        interface_0_microblaze_to_producer_rd_en_pin : out   std_logic;
        interface_0_producer_to_microblaze_data_pin  : in    std_logic_vector(0 to 31);

        -- Clock coming from the EDK system
        clock_generator_0_CLKOUT0_pin                : out   std_logic
        );
    end component;

    component producer
    port(
        clk             : in  std_logic; -- input frequency is 100 MHz
        reset           : in  std_logic; -- active high, comes from xps_gpio_0_GPIO_IO_O_pin(29)
        go              : in  std_logic; -- active high, comes from xps_gpio_0_GPIO_IO_O_pin(28)
        stop            : in  std_logic; -- active high, comes from xps_gpio_0_GPIO_IO_O_pin(27)
        producer_data_o : out std_logic_vector (0 to 31); -- data sent to interface.vhd
        producer_rdy    : out std_logic; -- '1' means there is a valid data to send to interface.vhd
        producer_rd_en  : in  std_logic  -- '1' means interface.vhd reads data
        );
    end component;
...
...
    -- Signal for asynchronous reset of interface.vhd in MicroBlaze
    signal interface_0_Rst_pin : std_logic;

    -- Control and data signals between MicroBlaze and custom HW consumer (consumer.vhd)
    -- Producer side in Microblaze
    signal interface_0_consumer_to_microblaze_rdy_pin   : std_logic;
    signal interface_0_microblaze_to_consumer_wr_en_pin : std_logic;
    signal interface_0_microblaze_to_consumer_data_pin  : std_logic_vector(0 to 31);

    -- Control and data signals between MicroBlaze and custom HW producer (producer.vhd)
    -- Consumer side in Microblaze
    signal interface_0_producer_to_microblaze_rdy_pin   : std_logic;
    signal interface_0_microblaze_to_producer_rd_en_pin : std_logic;
    signal interface_0_producer_to_microblaze_data_pin  : std_logic_vector(0 to 31);

    -- Global clock signal
    signal sys_clk : std_logic;

    -- signal coming from clock_generator (EDK) to feedback to GTX_CLK_0 of Hard Ethernet MAC
    signal clk_125_0000MHz_pin    : std_logic;

    -- Signal coming from GPIO
    signal xps_gpio_0_GPIO_IO_pin : std_logic_vector(0 to 31);

    -- Signals for PR module producer.vhd
    signal reset_producer  : std_logic;
    signal go_producer     : std_logic;
    signal stop_producer   : std_logic;

    -- Signals to be used in the BUFGCE to drive clock for PR module
    signal prmodule_clk_en : std_logic;
    signal prmodule_clk_in : std_logic;

    system_i : system
    port map (
        fpga_0_clk_1_sys_clk_pin                     => fpga_0_clk_1_sys_clk_pin,  --System clock
        fpga_0_rst_1_sys_rst_pin                     => fpga_0_rst_1_sys_rst_pin,  --System reset, active low
        fpga_0_RS232_Uart_1_RX_pin                   => fpga_0_RS232_Uart_1_RX_pin,
        fpga_0_RS232_Uart_1_TX_pin                   => fpga_0_RS232_Uart_1_TX_pin,
        fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin  => fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin,
        fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin    => fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin      => fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin    => fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin    => fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin   => fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin      => fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin    => fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin    => fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin,
        fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin   => fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin,
        fpga_0_Hard_Ethernet_MAC_MDC_0_pin           => fpga_0_Hard_Ethernet_MAC_MDC_0_pin,
        fpga_0_Hard_Ethernet_MAC_MDIO_0_pin          => fpga_0_Hard_Ethernet_MAC_MDIO_0_pin,
        fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin     => fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin,
        fpga_0_DDR2_SDRAM_DDR2_Clk_pin               => fpga_0_DDR2_SDRAM_DDR2_Clk_pin,
        fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin             => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
        fpga_0_DDR2_SDRAM_DDR2_CE_pin                => fpga_0_DDR2_SDRAM_DDR2_CE_pin,
        fpga_0_DDR2_SDRAM_DDR2_CS_n_pin              => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
        fpga_0_DDR2_SDRAM_DDR2_ODT_pin               => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
        fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin             => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
        fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin             => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
        fpga_0_DDR2_SDRAM_DDR2_WE_n_pin              => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
        fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin          => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin,
        fpga_0_DDR2_SDRAM_DDR2_Addr_pin              => fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQ_pin                => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
        fpga_0_DDR2_SDRAM_DDR2_DM_pin                => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQS_pin               => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin             => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
        fpga_0_SysACE_CompactFlash_SysACE_CLK_pin    => fpga_0_SysACE_CompactFlash_SysACE_CLK_pin,
        fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin  => fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin,
        fpga_0_SysACE_CompactFlash_SysACE_MPD_pin    => fpga_0_SysACE_CompactFlash_SysACE_MPD_pin,
        fpga_0_SysACE_CompactFlash_SysACE_MPA_pin    => fpga_0_SysACE_CompactFlash_SysACE_MPA_pin,
        fpga_0_SysACE_CompactFlash_SysACE_CEN_pin    => fpga_0_SysACE_CompactFlash_SysACE_CEN_pin,
        fpga_0_SysACE_CompactFlash_SysACE_OEN_pin    => fpga_0_SysACE_CompactFlash_SysACE_OEN_pin,
        fpga_0_SysACE_CompactFlash_SysACE_WEN_pin    => fpga_0_SysACE_CompactFlash_SysACE_WEN_pin,
        xps_gpio_0_GPIO_IO_O_pin                     => xps_gpio_0_GPIO_IO_pin,
        --clk_125_0000MHz_pin                        => clk_125_0000MHz_pin,
        --clk_125_0000MHz_pin_in                     => clk_125_0000MHz_pin_in,
        clock_generator_0_CLKOUT1_pin                => clk_125_0000MHz_pin,
        Hard_Ethernet_MAC_GTX_CLK_0_pin              => clk_125_0000MHz_pin,

        interface_0_Rst_pin                          => interface_0_Rst_pin,
        -- Control and data signals between MicroBlaze and custom HW consumer (consumer.vhd)
        interface_0_consumer_to_microblaze_rdy_pin   => interface_0_consumer_to_microblaze_rdy_pin,
        interface_0_microblaze_to_consumer_wr_en_pin => interface_0_microblaze_to_consumer_wr_en_pin,
        interface_0_microblaze_to_consumer_data_pin  => interface_0_microblaze_to_consumer_data_pin,

        -- Control and data signals between MicroBlaze and custom HW producer (producer.vhd)
        interface_0_producer_to_microblaze_rdy_pin   => interface_0_producer_to_microblaze_rdy_pin,
        interface_0_microblaze_to_producer_rd_en_pin => interface_0_microblaze_to_producer_rd_en_pin,
        interface_0_producer_to_microblaze_data_pin  => interface_0_producer_to_microblaze_data_pin,

        -- Clock coming out from the EDK system
        clock_generator_0_CLKOUT0_pin                => sys_clk
        );

    prmodule_clk_en     <= xps_gpio_0_GPIO_IO_pin(30);
    interface_0_Rst_pin <= xps_gpio_0_GPIO_IO_pin(29);
    reset_producer      <= xps_gpio_0_GPIO_IO_pin(29);
    go_producer         <= xps_gpio_0_GPIO_IO_pin(28);
    stop_producer       <= xps_gpio_0_GPIO_IO_pin(27);

    -- Clocking for the PR Module
    BUFGCE_pr_clk : BUFGCE
    port map (
        O  => prmodule_clk_in, -- Clock buffer ouptput, goes to clock of PR module
        CE => prmodule_clk_en, -- Clock enable input, coming from GPIO
        I  => sys_clk          -- Clock buffer input
        );

    prod : producer
    port map (
        clk             => prmodule_clk_in, -- input frequency is 100 MHz
        reset           => reset_producer,  -- active high, comes from xps_gpio_0_GPIO_IO_pin(29)
        go              => go_producer,     -- active high, comes from xps_gpio_0_GPIO_IO_pin(28)
        stop            => stop_producer,   -- active high, comes from xps_gpio_0_GPIO_IO_pin(27)
        producer_data_o => interface_0_producer_to_microblaze_data_pin, -- data sent to interface.vhd
        producer_rdy    => interface_0_producer_to_microblaze_rdy_pin,  -- '1' means there is a valid data to send to interface.vhd
        producer_rd_en  => interface_0_microblaze_to_producer_rd_en_pin -- '1' means interface.vhd reads data

The relevant parts of system.vhd generated by XPS:
...
...
begin

  -- Internal assignments

  dcm_clk_s <= fpga_0_clk_1_sys_clk_pin;
  sys_rst_s <= fpga_0_rst_1_sys_rst_pin;
  xps_gpio_0_GPIO_IO_O_pin <= xps_gpio_0_GPIO_IO_O;
  interface_0_Rst <= interface_0_Rst_pin;
  interface_0_consumer_to_microblaze_rdy <= interface_0_consumer_to_microblaze_rdy_pin;
  interface_0_microblaze_to_consumer_wr_en_pin <= interface_0_microblaze_to_consumer_wr_en;
  interface_0_microblaze_to_consumer_data_pin <= interface_0_microblaze_to_consumer_data;
  interface_0_producer_to_microblaze_rdy <= interface_0_producer_to_microblaze_rdy_pin;
  interface_0_microblaze_to_producer_rd_en_pin <= interface_0_microblaze_to_producer_rd_en;
  interface_0_producer_to_microblaze_data <= interface_0_producer_to_microblaze_data_pin;
  clock_generator_0_CLKOUT0_pin <= clk_100_0000MHzPLL0;

  microblaze_0 : microblaze_0_wrapper
    port map (
      CLK => clk_100_0000MHzPLL0,
      RESET => dlmb_LMB_Rst,
      MB_RESET => mb_reset,
      INTERRUPT => microblaze_0_Interrupt,
...
...
      Trace_MB_Halted => open,
      Trace_Jump_Hit => open,
      FSL0_S_CLK => open,
      FSL0_S_READ => interface_0_to_microblaze_0_FSL_S_Read,
      FSL0_S_DATA => interface_0_to_microblaze_0_FSL_S_Data,
      FSL0_S_CONTROL => interface_0_to_microblaze_0_FSL_S_Control,
      FSL0_S_EXISTS => interface_0_to_microblaze_0_FSL_S_Exists,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => microblaze_0_to_interface_0_FSL_M_Write,
      FSL0_M_DATA => microblaze_0_to_interface_0_FSL_M_Data,
      FSL0_M_CONTROL => microblaze_0_to_interface_0_FSL_M_Control,
      FSL0_M_FULL => microblaze_0_to_interface_0_FSL_M_Full,
      FSL1_S_CLK => open,
      FSL1_S_READ => open,
...
...
      ICACHE_FSL_IN_CLK => microblaze_0_IXCL_FSL_S_Clk,
      ICACHE_FSL_IN_READ => microblaze_0_IXCL_FSL_S_Read,
      ICACHE_FSL_IN_DATA => microblaze_0_IXCL_FSL_S_Data,
      ICACHE_FSL_IN_CONTROL => microblaze_0_IXCL_FSL_S_Control,
      ICACHE_FSL_IN_EXISTS => microblaze_0_IXCL_FSL_S_Exists,
      ICACHE_FSL_OUT_CLK => microblaze_0_IXCL_FSL_M_Clk,
      ICACHE_FSL_OUT_WRITE => microblaze_0_IXCL_FSL_M_Write,
      ICACHE_FSL_OUT_DATA => microblaze_0_IXCL_FSL_M_Data,
      ICACHE_FSL_OUT_CONTROL => microblaze_0_IXCL_FSL_M_Control,
      ICACHE_FSL_OUT_FULL => microblaze_0_IXCL_FSL_M_Full,
      DCACHE_FSL_IN_CLK => microblaze_0_DXCL_FSL_S_Clk,
      DCACHE_FSL_IN_READ => microblaze_0_DXCL_FSL_S_Read,
      DCACHE_FSL_IN_DATA => microblaze_0_DXCL_FSL_S_Data,
      DCACHE_FSL_IN_CONTROL => microblaze_0_DXCL_FSL_S_Control,
      DCACHE_FSL_IN_EXISTS => microblaze_0_DXCL_FSL_S_Exists,
      DCACHE_FSL_OUT_CLK => microblaze_0_DXCL_FSL_M_Clk,
      DCACHE_FSL_OUT_WRITE => microblaze_0_DXCL_FSL_M_Write,
      DCACHE_FSL_OUT_DATA => microblaze_0_DXCL_FSL_M_Data,
      DCACHE_FSL_OUT_CONTROL => microblaze_0_DXCL_FSL_M_Control,
      DCACHE_FSL_OUT_FULL => microblaze_0_DXCL_FSL_M_Full
    );
...
...
  microblaze_0_to_interface_0 : microblaze_0_to_interface_0_wrapper
    port map (
      FSL_Clk => clk_100_0000MHzPLL0,
      SYS_Rst => interface_0_Rst,
      FSL_Rst => microblaze_0_to_interface_0_FSL_Rst,
      FSL_M_Clk => clk_100_0000MHzPLL0,
      FSL_M_Data => microblaze_0_to_interface_0_FSL_M_Data,
      FSL_M_Control => microblaze_0_to_interface_0_FSL_M_Control,
      FSL_M_Write => microblaze_0_to_interface_0_FSL_M_Write,
      FSL_M_Full => microblaze_0_to_interface_0_FSL_M_Full,
      FSL_S_Clk => clk_100_0000MHzPLL0,
      FSL_S_Data => microblaze_0_to_interface_0_FSL_S_Data,
      FSL_S_Control => open,
      FSL_S_Read => microblaze_0_to_interface_0_FSL_S_Read,
      FSL_S_Exists => microblaze_0_to_interface_0_FSL_S_Exists,
      FSL_Full => open,
      FSL_Has_Data => open,
      FSL_Control_IRQ => open
    );

  interface_0_to_microblaze_0 : interface_0_to_microblaze_0_wrapper
    port map (
      FSL_Clk => clk_100_0000MHzPLL0,
      SYS_Rst => interface_0_Rst,
      FSL_Rst => interface_0_to_microblaze_0_FSL_Rst,
      FSL_M_Clk => clk_100_0000MHzPLL0,
      FSL_M_Data => interface_0_to_microblaze_0_FSL_M_Data,
      FSL_M_Control => net_gnd0,
      FSL_M_Write => interface_0_to_microblaze_0_FSL_M_Write,
      FSL_M_Full => interface_0_to_microblaze_0_FSL_M_Full,
      FSL_S_Clk => clk_100_0000MHzPLL0,
      FSL_S_Data => interface_0_to_microblaze_0_FSL_S_Data,
      FSL_S_Control => interface_0_to_microblaze_0_FSL_S_Control,
      FSL_S_Read => interface_0_to_microblaze_0_FSL_S_Read,
      FSL_S_Exists => interface_0_to_microblaze_0_FSL_S_Exists,
      FSL_Full => open,
      FSL_Has_Data => open,
      FSL_Control_IRQ => open
    );

  interface_0 : interface_0_wrapper
    port map (
      FSL_Clk => clk_100_0000MHzPLL0,
      FSL_S_Rst => microblaze_0_to_interface_0_FSL_Rst,
      FSL_M_Rst => interface_0_to_microblaze_0_FSL_Rst,
      FSL_S_Read => microblaze_0_to_interface_0_FSL_S_Read,
      FSL_S_Data => microblaze_0_to_interface_0_FSL_S_Data,
      FSL_S_Exists => microblaze_0_to_interface_0_FSL_S_Exists,
      FSL_M_Write => interface_0_to_microblaze_0_FSL_M_Write,
      FSL_M_Data => interface_0_to_microblaze_0_FSL_M_Data,
      FSL_M_Full => interface_0_to_microblaze_0_FSL_M_Full,
      Rst => interface_0_Rst,
      Clk => clk_100_0000MHzPLL0,
      consumer_to_microblaze_rdy => interface_0_consumer_to_microblaze_rdy,
      microblaze_to_consumer_wr_en => interface_0_microblaze_to_consumer_wr_en,
      microblaze_to_consumer_data => interface_0_microblaze_to_consumer_data,
      producer_to_microblaze_rdy => interface_0_producer_to_microblaze_rdy,
      microblaze_to_producer_rd_en => interface_0_microblaze_to_producer_rd_en,
      producer_to_microblaze_data => interface_0_producer_to_microblaze_data
    );

The contents of interface_v2_1_0.mpd:

BEGIN interface

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION LONG_DESC = Interface between FSL links (master and slave) and custom HW

## Bus Interfaces
BUS_INTERFACE BUS = SFSL, BUS_STD = FSL, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = MFSL, BUS_STD = FSL, BUS_TYPE = MASTER

## Peripheral ports
PORT FSL_Clk        = "",            DIR = I, SIGIS = CLK, BUS = SFSL:MFSL
#PORT FSL_Rst       = OPB_Rst,       DIR = I, SIGIS = RST, BUS = SFSL:MFSL
PORT FSL_S_Rst      = FSL_S_Rst,     DIR = I, BUS = SFSL
PORT FSL_M_Rst      = FSL_M_Rst,     DIR = I, BUS = MFSL
#PORT FSL_S_Clk     = FSL_S_Clk,     DIR = I, SIGIS = CLK, BUS = SFSL
PORT FSL_S_Read     = FSL_S_Read,    DIR = O, BUS = SFSL
PORT FSL_S_Data     = FSL_S_Data,    DIR = I, VEC = [0:31], BUS = SFSL
#PORT FSL_S_Control = FSL_S_Control, DIR = I, BUS = SFSL
PORT FSL_S_Exists   = FSL_S_Exists,  DIR = I, BUS = SFSL
#PORT FSL_M_Clk     = FSL_M_Clk,     DIR = I, SIGIS = CLK, BUS = MFSL
PORT FSL_M_Write    = FSL_M_Write,   DIR = O, BUS = MFSL
PORT FSL_M_Data     = FSL_M_Data,    DIR = O, VEC = [0:31], BUS = MFSL
#PORT FSL_M_Control = FSL_M_Control, DIR = O, BUS = MFSL
PORT FSL_M_Full     = FSL_M_Full,    DIR = I, BUS = MFSL

## External reset coming from GPIO
PORT Rst = "", DIR = I

## External clock coming from clock_generator in EDK
PORT Clk = "", DIR = I

#Signals from Microblaze as producer connected to external custom HW consumer
#Incoming data from FSL_S_Data of Microblaze will be directed to custom HW consumer
PORT consumer_to_microblaze_rdy   = "", DIR = I
PORT microblaze_to_consumer_wr_en = "", DIR = O
PORT microblaze_to_consumer_data  = "", DIR = O, VEC = [0:31]

#Signals from external custom HW producer connected to Microblaze as consumer
#Incoming data from custom HW producer will be directed to FSL_M_Data of MicroBlaze
PORT producer_to_microblaze_rdy   = "", DIR = I
PORT microblaze_to_producer_rd_en = "", DIR = O
PORT producer_to_microblaze_data  = "", DIR = I, VEC = [0:31]

END

Any help would be appreciated.

Regards,
Aurelio

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