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Observer
Observer
4,084 Views
Registered: ‎05-16-2008

Separate clock for custom IP

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Hi,

 

I want to make a design, where some components of my custom IP run on a clock with a higher frequency than plb_bus which connects the IP to to the processor. 

Any suggestions?

 

cheers, 

Omar

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Xilinx Employee
Xilinx Employee
4,866 Views
Registered: ‎08-07-2007

Hi Omar,

 

Another option is to generate another clock output with the clock generator and connect that clock into your custom peripheral.

 

-XF

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Scholar
Scholar
4,069 Views
Registered: ‎04-07-2008

You can instantiate a PLL or DCM into your IPIF module.  Or if the clock is coming from a oscillator I am pretty sure you can just add

a Input into the IPIF and instantiate a clock buffer in the IPIF.

Message Edited by golson on 05-24-2009 03:18 AM
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Xilinx Employee
Xilinx Employee
4,867 Views
Registered: ‎08-07-2007

Hi Omar,

 

Another option is to generate another clock output with the clock generator and connect that clock into your custom peripheral.

 

-XF

View solution in original post

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Observer
Observer
3,974 Views
Registered: ‎05-16-2008

Hi,

 

I tried out the suggestion. I generated a new clock output with 250Mhz and inputed it into my custom IP. My DCM clock input is set to 100Mhz and the bus clock outputed from the DCM module is also set to 100Mhz, but i got a timing error when generating a bit file. 

 

When i changed the DCM input clock to 250Mhz, I didn't get the timing error but something seems to be wrong with the UART ip in my design: A simple "print" function isn't outputed in the hyperterminal.  

 

'Thanks in Advance,

Omar

 

 

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