UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
2,881 Views
Registered: ‎12-15-2016

Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

I need to set a GPIO pin from FSBL.

I am currently patching the psu_init* files after creation (The mask write), though would expect that I could control this from Vivado. I cannot to find a place to control the direction.

Opening the Zynq UltraScale+ MPSoC IP core, gives access to Peripheral -> Low Speed -> I/O Peripherals -> GPIO and then the GPIO pins. The direction is fixed on inout and I cannot set the default direction / level.

Is there not a way for controlling GPIO to FSBL?

0 Kudos
1 Solution

Accepted Solutions
Adventurer
Adventurer
3,900 Views
Registered: ‎12-15-2016

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

Thanks for all your input.

Though need the GPIO to be part of the psu_init as they enable clocks used for pll locking later in the sequence.

 

So still hope for the HDF to contain the initial GPIO level in future version of Vivado.

 

Regards

Claus

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
2,864 Views
Registered: ‎02-26-2014

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

Hi,

 

In FSBL we generally enable GPIO, but not define the direction and the value (if it is output).

They are done in the application. Following are the bare metal APIs to set the direction and the value to GPIO.

 

XGpioPs_SetDirectionPin(&Gpio, Output_Pin, 1);
XGpioPs_SetOutputEnablePin(&Gpio, Output_Pin, 1);

 

XGpioPs_WritePin(&Gpio, Output_Pin , 0x1);

 

Regards,

Ravi

0 Kudos
Adventurer
Adventurer
2,849 Views
Registered: ‎12-15-2016

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

Thanks for your reply.

 

Unfortunately I need this to be done in the FSBL, so will continue to patch the FSBL.

 

Why not give option for defining direction and value in Vivado project?

 

I think you are doing this for the AXI-GPIO IP core.

 

Regards

Claus

0 Kudos
Xilinx Employee
Xilinx Employee
2,815 Views
Registered: ‎02-26-2014

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

Hi,

 

You can try doing the same on FSBL. Add this functionality in the standard FSBL project provided by SDK.

The APIs that I mentioned are for PS GPIO.

Have a look at PS GPIO driver.

 

Regads,

Ravi

0 Kudos
Moderator
Moderator
2,803 Views
Registered: ‎09-12-2007

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution
Add the code to fsbl hooks fallback. You can use the xil_Out()

See wiki page here where I did something similar
http://www.wiki.xilinx.com/Execute+Microblaze+Application+from+PS+DDR
Adventurer
Adventurer
3,901 Views
Registered: ‎12-15-2016

Re: Set MIO GPIO pin on ZynqMP from FSBL

Jump to solution

Thanks for all your input.

Though need the GPIO to be part of the psu_init as they enable clocks used for pll locking later in the sequence.

 

So still hope for the HDF to contain the initial GPIO level in future version of Vivado.

 

Regards

Claus

0 Kudos