The Interrupt Controller ignores some Custom IP interrupts

[jmpg]

Hello,

I have a problem with a custom IP interrupt. I hope someonecan help me, please.

I'm trying to develop an application based on Xilkernel OSto support LWIP socket mode. The core functionality of the application isinterrupt-driven, based on two interrupts generated by the custom IP.

Everything works near perfectly. The event handlers manageevery Interrupt as expected. Nevertheless, there are interrupts generated bythe custom IP that sometimes doesn't trigger an interrupt event.

This happens rarely, but there are some interruptsmissing/ignored, and it causes a big problem on the application purpose.

I have connected the IRQ port of the INTC and the custom IPinterrupts to digital probes of my OSC, so I can see and check that the customIP generates the proper interrupts but the INTC ignores them (very few times).

Any suggestion, test procedure or idea are very welcome.

The details of my EDK project are the followings

• It mainly consists of an Interrupt controller, Timer, Ethernet, ... and the custom IP

• The Timer, Ethernet (2), the custom IP(2) have interrupt signals connected to the INTC, as described in the MHS file

BEGIN xps_intc

 PARAMETER INSTANCE = xps_intc_0

 PARAMETER HW_VER = 1.00.a

 PARAMETERC_BASEADDR = 0x81800000

 PARAMETER C_HIGHADDR = 0x8180ffff

 BUS_INTERFACE SPLB = mb_plb

 PORT Irq = Interrupt

 PORT Intr = Ethernet_MAC_IP2INTC_Irpt & xps_timer_1_Interrupt& fpga_0_Ethernet_MAC_MDINT & out_intrb & out_intra

END

• The custom MPD file has the interrupt signals defined as:

PORT out_intra = "", DIR= O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

PORT out_intrb = "", DIR= O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

• Finally, the interrupt signals have a pulse width around 10times wider than the system clock.  So, it has a great margin to comply theTiming requirement of the INTC (according to its datasheet the signal must remainstable for a minimum interval to guarantee capture. the interval must be atleast an XPS INTC clock period plus a suitable margin. The margin is chosen byspecification to be 20% of the XPS INTC clock period)

Thanks in advance!

José 

[drjohnsmith]

Hi

is the INTC getting other interupts ?

  if so are you clearing them quick enough to catch the next one ?

      make small as possible stub tests for all interupts, that just woggle a pin,  see if they are being missed then.

[jmpg]

Hi,

Thanks for replying, 

Yes, the INTC has an interrupt each 10 ms generated by the Timer (It is the kernel ticks used by Xilkerner for scheduling). I've tested also with a period of 20 ms, but the problem is the same.

I forgot some information about the problem:

The custom IP interrupts has a period around 38 ms (out_intrb happens and then out_intrb 38 ms before and so on), and the interrupt handler is very simple, and it is performed in few tens of microseconds (I have flags connected to FPGA pins to be able to see on the OSC the timing of the application) 

Sorry, I don't understand very well your suggestion= "make small as possible stub tests for all interupts, that just woggle a pin,  see if they are being missed then" 

regards, 

[drjohnsmith]

HI

if you have one interupt every 10 ms that takes a ms or two to service, and another every 38 ms, that takes 'a few 10 of ms' to service,  your in close terratory to miss an interupt.

just depends what else is going on withthe processor, 

  Have you cache enabled ? DMA or whatever,

     are you certain you have the bandwidth.

So suggestion was to minimise all the interupt routines C code.

   just toggle a pin in each interupt routine, so you can see each interupt happen on the scope.

i.e. keep each interupt routine to a ms or less is a good iea.

    use the interupt to set a flag , mailbox or what have you then get out of it again.

[jmpg]

Hi,

The Interrupt service takes a few tens of microseconds, not milli.  it is a very simple routine, as you propose, the intr handler just changes a flag (to see it on the OSC) and do very few computation (I think it takes less than 100 us)

And yes, uB has the cache enabled, but  It doesn't use DMA for anything (the Ethernet is not the most demanding service of the application) 

I think the SW meet timing constraints, since I can see spare time between interrupts. 

 I have worked in other projects with the 10 ms ticks and higher interrupts rate generated by custom IP (with period near 1 ms), I'm almost sure that Xilkernel scheduling service doens't take more than few us (micro). 

Thanks for your contribution!

regards, 

Message Edited by jmpg on 04-27-2010 10:19 AM

[drjohnsmith]

Hi  sorry

missed micro,  not milli

well then, what could be causing the interupt to be missed ?

   two happen at the same time should be ok,

      you are clearing the interupt, set it for edge, so that should be ok as your not re triggering,

 youve done what I would have done, just toggle the flags in the interupt routine, can't get much simpler than that can you !

[jmpg · Accepted solution]

Hello, 

I achieved to workaround my problem. I added a intermediate flip-flop between my custom IP (interrupt generator) and the INTC. In this flip-flop, the signals is upsampled to the sys_clock domain, and now it is working smoothly.

I'll read the Interrupt App Note to try to find other problems, thanks!

Best regards,

Hello, 
I achieved to workaround my problem.

I added a intermediate flip-flop between my custom IP (interrupt generator) and the INTC. In this flip-flop, the signals is upsampled to the sys_clock domain, and now it is working smoothly.

Best regards,

[nola94]

Hello,

I would like to send data from my custom IP(IPIF read FIFO) to my pc through ethernet(xps_ethernetlite). I am using LWIP.

How can i use the Custom IP interrupt( when FIFO if full an interrupt event is occured and is ready to send data) along with others interrupts of the system(timer interrupt, ethernet interrupt). I am using the TxTest.c source code found on Xapp1026 for implement the LWIP.

Any help?

Some source code include LWIP implementation?

Regards,

Lefteris

[jmpg]

Hello,

I think the appnote you metioned is a good reference of how to use LWIP. 

To manage several interrupts you must add an Interrupt Controller, I think the XAPP778 can be very useful (Using and Creating Interrupt-Based Systems)

I don't know how you generated your custom IP, but one important thing is to identify the interrupting signals.

If you have used the "Create and Import Peripheral Wizard" from EDK, you have one step called "Importing an Existing Peripheral" (Platform Studio)

When you are importing the peripheral (your custom IP), you can select some signals as interrupting signal.

An alternative is to modify the MPD (Microprocessor Peripheral Definition) files directly. In your custom IP, there should be a folder called "data". There must be a file like "customIP.mpd".

This file contains the ports declaration of your custom IP. Your interrupting signal must appear like:

PORT IP2INTC_Irpt = ““, DIR = O, SIGIS = INTERRUPT,SENSITIVITY = EDGE_RISING 

You can learn more about the MPD syntax on:

"Platform Specification Format Reference Manual"

So, once you achieve a interrupt driven system (HW ok), you can develop some interrupt service in charge of read the FIFO data and send it throughout Ethernet (here you should look for LWIP doc or maybe you can use the BSD interface if you add the Xilkernel OS to your SW platform)

I hope the answer can help you :smileyhappy:,

Best regards,

Jose

[nola94]

Thank you for the information,

Maybe i was not clear about what i am searching for...

I would like to manage my interrupts in software....

Any useful documentation?

The code about Lwip is complicated and dont know how to add the interrupt from custom IP inside this code (Xapp1026)

Regards,

Lefteris

[jmpg]

Hello,

Well, the XAPP778 (Using and Creating Interrupt-Based Systems) explains some functions of the Interrupt Controller driver and also an application example.

best regards,

Jose

[nola94]

Hello Jose,

thank you, i'll take a look an the application...

Lefteris