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Contributor
Contributor
6,534 Views
Registered: ‎01-07-2014

Timing parameters generation error

 

I synthesize Zynq-based design, with ps7 subsystem

Vivado 2014.2/linux 64bit platform

 

  All of the sudden, on a working design, I started to get lots of the following messages:

 

[Netlist 29-73] Incorrect value '10.000000' specified for property 'CLKFBOUT_MULT_F'. The system will either use the default value or the property value will be dropped. Verify your source files. ["/design/nvmtop2/.Xil/Vivado-21578-cwserver/dcp/nvme_zynq_wrapper.edf":253755]

[Netlist 29-73] Incorrect value '0.000000' specified for property 'CLKFBOUT_PHASE'. The system will either use the default value or the property value will be dropped. Verify your source files. ["/design/nvmtop2/.Xil/Vivado-21578-cwserver/dcp/nvme_zynq_wrapper.edf":253756]

 

Those are qualified as critical warnings. They pop up when I open the synthesized design. The synthesis

itself goes normally.

 

After getting those warnings, the implementation does not go through, citing numerous timing parameter and check

errors.

 

Having looked for the source of this issue, I found out that my PS7 clock settings are

completely corrupted.

 

I attached my ARM/DDR clock values I get. They are at 660/528 MHZ respectively, not at all what they should be: 667/533MHz. Also: ranges are out

 

Looking at Advanced settings tab, I find that my PLL divisors settings are the following:

 

ARM PLL = 40

DDR PLL = 32

IOPLL = 54

 

At the same time, the ARM PLL Freq = 1320 MHZ !!!!  

(DDR clock = 1056M, IO = 1782M)

 

      How could this happen? 33.3333 X 40 = 1333.33MHz ?  

 

This is the reaso, I think, for wrong PLL divisor values and timing checks pb.

It looks like Vivado started to round down all clock values. What's more, I cannot override

clocks and divisor values, Vivado keeps enforcing wrong ones.

 

Any ideas on what could be causing this project database corruption?

 

What cold be done to reset PS7 clock settings without restarting anew the project?

(whan I apply default board preset for ZC706 nothing happens)

 

 

 

 

 

 

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5 Replies
Xilinx Employee
Xilinx Employee
6,511 Views
Registered: ‎05-14-2008

Re: Timing parameters generation error

This could be better resolved on the "Embbeded Development Tools" board. I'll move your post to that board.

 

-Vivian

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Xilinx Employee
Xilinx Employee
6,495 Views
Registered: ‎08-02-2007

Re: Timing parameters generation error

Hi,

 

Would that be possible to share your design?

 

--Hem

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Contributor
Contributor
6,481 Views
Registered: ‎01-07-2014

Re: Timing parameters generation error

Hi Hem,

 

  Sure, here's the simple design illustrating the problem. See processing system clock parameters: basic and advanced

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Visitor gomiz3
Visitor
5,906 Views
Registered: ‎06-18-2014

Re: Timing parameters generation error

Hi,

The problem may be your "locale"  lenguage setting. So Xilinx may be mistaking dots and commas. 

It is better explained here:

http://www.xilinx.com/support/answers/44257.html

 

best regards

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Adventurer
Adventurer
5,835 Views
Registered: ‎03-13-2015

Re: Timing parameters generation error

This is also a problem on windows and Vivado 2014.4. I worked around this problem using window's applocale utility.
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