cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
327 Views
Registered: ‎10-03-2019

Transfer the contents of DDR3 Memory to AXI BRAM

I have taken the XAPP1026 reference design for Artix-7 and created the Application Project for LWIP UDP server in Vivado v2018.2. I am sending packets from Packet sender and receiving the same and I am observing that the Payload data is stored in a variable in DDR3 memory. I want to transfer the payload data from DDR3 memory to Block RAM memory in FPGA for further processing. To do the same I have added one AXI BRAM as a Peripheral to Microblaze. I have used memcpy function for transfer of data from DDR3 to AXI BRAM, but the memory locations in AXI BRAM are reflecting the Garbage value instead of UDP Payload data.

Can you suggest some scheme to fulfil my requirement???

0 Kudos
Reply
1 Reply
Moderator
Moderator
266 Views
Registered: ‎10-30-2017

Hi manasam@bel.co.in ,

Please add the ila on BRAM interface and check once that the data is copying from DDR to BRAM is correct or not. I think the data might be copied in byte reverse order. compare BRAM data with original data (data in DDR) to check any byte reversal has happned. 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

0 Kudos
Reply